Method for manufacturing semiconductor memory and method for manufacturing capacitor
AssigneeNEC Corporation
InventorTomoe Yamamoto
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor memory cell is provided. The semiconductor memory cell can include a memory cell transistor (10) and a capacitor. The capacitor can be formed in a groove (13) formed in an interlayer insulation film (12). The capacitor can have a lower electrode including a selective growth film (18) which may be selectively deposited on a lower electrode film (16). Selective growth film (18) can be a ruthenium film having a thickness of approximately 5˜10 nm and may serve as a buffer which may prevent lower electrode and a capacitor insulation film (20) from deterioration in integrity which could cause increased leakage currents.
Claims20
A method for manufacturing a semiconductor memory having an array of memory cells, each memory cell including a memory cell transistor electrically connected to a capacitor, comprising the steps of:
- forming a memory cell transistor on a semiconductor substrate followed by forming a first interlayer insulation film over a surface resulting after forming the memory cell transistor;
- forming a groove for making the capacitor at a predetermined location in the first interlayer insulation film;
- forming a lower electrode film over a surface resulting from forming the groove;
- applying and processing a resist material so as to leave a resist film in the groove;
- removing excess portions of the lower electrode film so as to leave the lower electrode film in the groove;
- selectively forming a first metal film on the lower electrode film;
- and
- forming a capacitor insulation film and an upper electrode film over a surface resulting from removing excess portions of the lower electrode film.
A method for manufacturing a semiconductor memory having an array of memory cells, comprising the steps of:
- forming a memory cell transistor on a semiconductor substrate followed by forming a first interlayer insulation film over a surface resulting after forming the memory cell transistor;
- forming a capacitor contact hole in the first interlayer insulation film to expose a first diffusion region of the memory cell transistor;
- forming a capacitor contact electrically connected to the first diffusion region;
- forming a second interlayer insulation film on the first interlayer insulation film;
- forming a groove for making a capacitor at a predetermined location in the second interlayer insulation film;
- forming a lower electrode film over a surface resulting from forming the groove;
- applying and processing a resist material so as to leave a resist film in the groove;
- removing excess portions of the lower electrode film so as to leave the lower electrode film in the groove;
- selectively forming a first conductive film on the lower electrode film;
- and
- forming a capacitor insulation film and an upper electrode film over a surface resulting from removing excess portions of the lower electrode film.
A method for manufacturing a capacitor formed on a semiconductor substrate, comprising the steps of:
- forming a first interlayer insulation film over a surface of the semiconductor substrate;
- forming a groove for making the capacitor at a predetermined location in the first interlayer insulation film;
- forming a lower electrode film over a surface resulting from forming the groove;
- applying and processing a resist material so as to leave a resist film in the groove;
- removing excess portions of the lower electrode film so as to leave the lower electrode film in the groove;
- forming a conductive film on the lower electrode film;
- and
- forming a capacitor insulation film and an upper electrode film over a surface resulting from removing excess portions of the lower electrode film.
Dependencies are inferred from the claim text.