Method of manufacturing semiconductor device
AssigneeNEC Corporation
InventorAtsuki Ono
Life of this patent
Estimating the term…
Abstract
The relationship between the difference between design and measured values of the gate length of a gate electrode of a transistor and the dose of an impurity to be injected into SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values is formulated. The gate length of the gate electrode which is produced by photolithography and etching process is measured. The dose of the impurity to be injected into the SD extension regions or the pocket regions is adjusted to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.
Claims6
A method of manufacturing a semiconductor device having a transistor with SD extension regions and pocket regions, comprising the steps of:
- formulating the relationship between the difference between design and measured values of a gate length of a gate electrode of the transistor and a dose of an impurity to be injected into the SD extension regions which is necessary to equalize characteristics of the transistor to design values;
- measuring the gate length of the gate electrode which is produced by photolithography and etching process;
- and
- adjusting the dose of the impurity to be injected into said SD extension regions to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.
A method of manufacturing a semiconductor device having a transistor with SD extension regions and pocket regions, comprising the steps of:
- formulating the relationship between the difference between design and measured values of a gate length of a gate electrode of the transistor and a dose of an impurity to be injected into the pocket regions which is necessary to equalize characteristics of the transistor to design values;
- measuring the gate length of the gate electrode which is produced by photolithography and etching process;
- and
- adjusting the dose of the impurity to be injected into said pocket regions to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.
Dependencies are inferred from the claim text.