Method for checking a semiconductor memory device

Abstract

A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.

Dependencies are inferred from the claim text.