Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
AssigneeMicron Technology, Inc.
InventorsFernando Gonzalez, Francis L. Benistant
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Abstract
A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.
Claims61
A memory cell comprising:
- a word line;
- first and second digit lines;
- and,
- a transistor comprising a control gate region connected to said word line, source and drain regions respectively connected to said first and second digit lines, and at least first and second floating gate regions located beneath said control gate region.
A method of forming a memory cell comprising the steps of:
- forming a first floating gate region on a silicon substrate;
- forming a second floating gate region on said silicon substrate;
- said second floating gate region being adjacent to and electrically isolated from said first floating gate region;
- forming an insulating layer over said first and second floating gate regions;
- forming a control gate region over said insulating layer and over said first and second floating gate regions;
- forming source and drain regions in said substrate such that said first and second floating gate regions are located at least in part between said source and drain regions;
- and
- forming electrical interconnects with said source, drain and control gate regions.
A computer system comprising:
- a processor and a flash memory connected to said processor for storing information used by said processor, said flash memory comprising a plurality of arrayed memory cells, at least some of said arrayed memory cells comprising:
- a word line;
- first and second digit lines;
- and,
- a transistor comprising a control gate region
- connected to said word line, source and drain regions respectively connected to said first and second digit lines, and at least first and second floating gate regions located beneath said control gate region.
A method of operating a memory cell comprising a first and second floating gate regions, a control gate region, source and drain regions, a word line connected to said control gate region, and first and second digit lines respectively connected to said source and drain regions, to store a multi-bit binary value in said memory cell, said method comprising the steps of:
- (a) controlling the selective storage of charges in said first and second floating gate regions to store a multi-bit binary value in said memory cell;
- and
- (b) selectively reading the charges stored in said first and second floating gates region and using the read charges to determine a multi-bit binary value stored in said memory cell.
Dependencies are inferred from the claim text.