Electrically alterable non-volatile memory with n-bits per cell
OwnerGerald J. Banksinventor
Life of this patent
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Abstract
A multi-bit memory device with a memory cell means for storing input information for an indefinite period of time. The multi-bit memory means stores information in up to Kn memory states (Kn>1). A memory cell programming means and comparator means is also included. The present multi-bit memory device also includes a voltage divider arrangement with pull-up devices in a memory array to provide stable and accurate reference voltages over process, temperature, and voltage variations.
Claims1
For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising:
- settling a voltage threshold value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and
- reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell,
- wherein the operation for settling the voltage threshold value of the one non-volatile multi-level memory cell includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programing pulse supplied to the bit line, and
- wherein the program operation of the one non-volatile multi-level memory cell is carried out by a plurality of programming pulses, the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first electric parameter and the second programming pulse has a second electric parameter so that a first voltage threshold value change of the one non-volatile multi-level memory cell between after applying the first programming pulse and before applying the first programming pulse is substantially larger than a second voltage threshold value change of the one non-volatile multi-level memory cell between after applying the second programming pulse and before applying the second programming pulse.
Dependencies are inferred from the claim text.