Dynamic flop with power down mode
AssigneeSun Microsystems, Inc.
InventorJaya Prakash Samala
Life of this patent
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Abstract
A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.
Claims14
A dynamic flip-flop circuit comprising:
- a first latch having a first input lead, a second input lead, and an output lead, said first latch including a first shutoff circuit, said first shutoff circuit including a first nand gate, a first inverter, and a first n-channel transistor, said first nand gate having a first input lead and a second input lead, said first input lead coupled to an output lead of a second latch, and said second input lead coupled to a compare enable line, said first inverter having an input lead and an output lead, said input lead coupled to said output lead of said first nand gate, and said first n-channel transistor having a first lead coupled to said output lead of said first inverter and a second lead coupled to said output lead of said first latch;
- and
- said second latch having an input lead and an output lead, said second latch further including a second shutoff circuit, said second shutoff circuit including a second nand gate, a second inverter, and a second n-channel transistor, said second nand gate having a second input lead and a second input lead, said second input lead coupled to said output lead of said first latch, and said second input lead coupled to said compare enable line, said second inverter having an input lead and an output lead, said input lead coupled to said output lead of said second nand gate, and said second n-channel transistor having a second lead coupled to said output lead of said second inverter and a second lead coupled to said output lead of said second latch.
A dynamic flip-flop circuit comprising:
- a first latch having a first input lead, a second input lead, a third input lead, and an output lead, said first latch including a shutoff circuit, wherein
- said first input lead of said first latch is coupled to receive a clock signal;
- said second input lead of said first latch is coupled to receive a data signal;
- said third input lead of said first latch is coupled to receive a compare enable signal;
- said first latch is operative to output a signal of a first logic level at said output lead of said first latch when said clock signal is low;
- said first latch is operative to sample a logic level at said second input lead of said first latch when said data signal is high and said clock signal is high;
- and
- said first shutoff circuit is operative to cause said first latch to stop sampling when said data signal is high and said clock signal is high, unless said compare enable signal is low.
- a second latch having an input lead and an output lead, said second latch including a second shutoff circuit, wherein
- said second latch is operative to output a signal of said first logic level at said output lead of said second latch when both said clock signal is low;
- said first input lead of said second latch is coupled to receive said clock signal;
- and
- said second input lead of said second latch is coupled to receive a complement of said data signal;
- said first latch is operative to output a signal of a first logic level at said output lead of said first latch when both said clock signal is low;
- said first latch is operative to sample a logic level at said second input lead of said first latch when said data signal is high and said clock signal is high;
- and
- said first shutoff circuit is operative to cause said first latch to stop sampling when said data signal is high and said clock signal is high, unless said compare enable signal is low.
- a first output latch having an input lead and an output lead, said input lead of said first output latch coupled to said output lead of said first latch;
- and
- a second output latch having an input lead and an output lead, said input lead of said second output latch coupled to said output lead of said second latch.
Dependencies are inferred from the claim text.