Clock routing in multiple channel modules and bus systems

A non-terminating apparatus comprising:

• a first non-terminating module having at least one integrated circuit;
• a second non-terminating module having at least one integrated circuit;
• and
• a flexible interface operatively connecting the first and the second non-terminating modules and configured to carry timing signals directly there between and also between the at least one integrated circuits on both the first and the second non-terminating modules.

A non-terminating apparatus comprising:

• a first non-terminating module having at least one integrated circuit;
• a second non-terminating module having at least one integrated circuit;
• and
• a flexible interface operatively connecting the first and the second non-terminating modules and configured to carry timing signals between the at least one integrated circuits on both the first and the second non-terminating modules.

An apparatus comprising:

• a memory interface circuit;
• a clock signal generating circuit;
• a plurality of memory modules, each having memory circuitry thereon, the memory modules being operatively coupled and arranged in an order, wherein the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit, and the memory module positioned at the end of the order includes a clock signal terminating circuit, and
• wherein a clock loop is formed by initially directly routing a clock signal from the output of the clock signal generating circuit through each of the memory modules in the order to the memory module positioned at the end of the order without asserting the clock signal on the memory circuitry, then routing and asserting the clock signal back through the memory modules and the memory circuitry thereon in reverse order to the memory module positioned at the beginning of the order and from there to the memory interface circuit, then routing and asserting the clock signal from the memory interface circuit back through the memory modules and memory circuitry thereon in order to the memory module positioned at the end of the order, and then terminating the clock signal at the clock signal terminating circuit.

An apparatus comprising:

• a circuit board;
• at least one clock generating circuit mounted on the circuit board;
• a first connector, a second connector and a third connector mounted on the circuit board.
• a first conductor connecting an output node of the clock generating circuit with the first connector;
• a first non-terminating memory circuit card operatively arranged in the first connector and configured to receive a timing signal as output by the clock generating circuit and provided via the first conductor and first connector;
• a second non-terminating memory circuit card operatively arranged in the second connector.
• a flexible conductor coupled between the first and second non-terminating memory circuit cards and configured to carry the timing signal from the first non-terminating memory card to the second non-terminating memory card;
• a second conductor connecting the second connector with the third connector;
• a terminating memory card operatively arranged in the third connector and configured to receive the timing signal from the second non-terminating memory card via the second connector, the second conductor and third connector.

An apparatus comprising:

• a circuit board;
• at least one clock generating circuit mounted on the circuit 4 board;
• a first connector, a second connector and a third connector mounted on the circuit board.
• a first conductor connecting an output node of the clock generating circuit with the first connector;
• a first non-terminating memory circuit card operatively arranged in the first connector and configured to receive a timing signal as output by the clock generating circuit and provided via the first conductor and first connector;
• a second conductor connecting the first connector with the second connector;
• a second non-terminating memory circuit card operatively arranged in the second connector and configured to receive the timing signal from the first non-terminating memory circuit card via the second conductor and second connector.
• a third conductor connecting the second connector with the third connector;
• a terminating memory card operatively arranged in the third connector and configured to receive the timing signal from the second non-terminating memory card via the second connector, the third conductor and third connector.

A method for routing a clock signal in a device capable of supporting multiple memory modules, the method comprising:

• generating a clock signal;
• directly passing the clock signal to a terminating memory module;
• configuring the terminating memory module to provide the clock signal to at least one memory integrated circuit provided on the terminating memory module;
• then
• routing the clock signal from the terminating memory module to a memory interface circuit and then from the memory interface circuit back to the terminating memory module;
• and then
• terminating the clock signal at the terminating memory module.