Shared memory graphics accelerator system

An integrated graphics display memory element utilizable in a graphics accelerator system that provides graphics display data to a display element for display thereby, wherein the graphics accelerator system includes a central processing unit that generates graphics display data and graphics commands for processing graphics display data and an off-chip frame buffer memory element having a first refresh frequency requirement, the integrated graphics display memory element comprising:

• a graphics accelerator that can be connected to receive graphics display data and graphics commands from the central processing unit via a CPU data bus and a control signal bus, respectively;
• a data distribution bus connected to the graphics accelerator;
• an on-chip frame buffer memory element connected to the data distribution bus for receiving graphics display data from the graphics accelerator;
• an output data storage element connected to the data distribution bus for receiving graphics display data from the graphics accelerator and the on-chip frame buffer memory element as output display data,
• the off-chip frame buffer memory element being connectable to the data distribution bus for providing graphics display data to the output data storage element as output display data.

A graphics accelerator system that provides graphics display data to a display element for display thereby, the graphics accelerator system comprising:

• a central processing unit that generates graphics display data and graphics commands for processing graphics display data;
• at least one integrated graphics display memory element that includes
• (i) a graphics accelerator connected to receive graphics display data and graphics commands from the central processing unit via a CPU data bus and a control signal bus, respectively, connected therebetween;
• (ii) an on-chip frame buffer memory element connected to receive graphics display data from the graphics accelerator via a data distribution bus connected therebetween;
• and
• (iii) an output data storage element connected to the data distribution bus for receiving display data from both the graphics accelerator and the on-chip frame buffer memory element as output display data;
• an off-chip frame buffer memory element connected to receive graphics display data from the graphics accelerator via the data distribution bus and to provide graphics display data to the output data storage element as output display data;
• random access memory digital-to-analog converter (RAMDAC) means for converting output display data received from the output data storage element via an output bus connected therebetween to display output signals;
• and
• a display element that responds to display output signals received from the RAMDAC means by providing a corresponding visual display.

A shared memory graphics accelerator system that provides graphics display data to a display element for display thereby, the shared memory graphics accelerator system comprising:

• a central processing unit that generates graphics display data and graphics commands for processing graphics display data;
• an integrated graphics display memory element that includes both a graphics accelerator connected to receive graphics display data and graphics commands from the central processing unit and an on-chip frame buffer memory element connected to receive graphics display data from the graphics accelerator via a display data distribution bus;
• and
• an off-chip frame buffer memory element connected to receive graphics display data from the graphics accelerator via the data distribution bus;
• wherein the graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on pre-defined display data distribution criteria.