US 2001/0040475 A1Published application

Integrated circuit

AssigneeNEC Corporation

InventorHiroki Inohara

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Abstract

An IC (Integrated Circuit) including internal circuitry to which a multiphase clock is distributed includes 1/n clock, main wiring drivers each including a frequency divider for dividing the frequency of an input clock by n and a drive circuit for delivering the resulting 1/n clock to a corresponding 1/n clock main wiring. Normal clock, main wiring drivers each include a delay for delaying an input clock to thereby output a normal clock and a drive circuit for delivering the normal clock to a corresponding normal clock main wiring. A clock distributing circuit includes clock wirings for distributing a clock input via a clock input circuit and a plurality of repeat buffers for distributing the distributed clock to each of the 1/n clock and normal clock, main wiring drivers. The IC additionally includes a wiring wiring the outputs of the repeat buffers, a wiring wiring the outputs of 1/n clock, main wiring drivers, and wiring wiring the outputs of the normal clock, main wiring drivers.

Claims15

Dependent claims

An IC (Integrated Circuit) including internal circuitry to which a multiphase clock is distributed, said IC comprises:

a plurality of 1/n clock, main wiring drivers each including frequency dividing means for dividing a frequency of an input clock by n (n being a positive integer) to thereby output a 1/n clock and drive means for delivering said 1/n clock to a corresponding 1/n clock main wiring;
a plurality of normal clock, main wiring drivers each including delay means for delaying an input clock to thereby output a normal clock and drive means for delivering said normal clock to a corresponding normal clock main wiring;
a clock distributing circuit including lock wirings for distributing a clock input via a clock input circuit and a plurality of repeat buffers for distributing said clock distributed to each of said plurality of 1/n clock, main wiring drivers and said plurality of normal clock, main wiring drivers;
a wiring wiring outputs of all of said plurality of repeat buffers;
a wiring wiring outputs of all of said plurality of 1/n clock, main wiring drivers;
and
a wiring wiring outputs of all of said plurality of normal clock, main wiring drivers.

4 more elements

Dependencies are inferred from the claim text.