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US 2001/0040474 A1Published application
Clock control method and circuit
AssigneeNEC Corporation
InventorTakanori Saeki
Life of this patent
Estimating the term…
Abstract
A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.
Claims59
A clock control circuit comprising
- at least one timing averaging circuit which generates and outputs from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively from first and second input terminals, at a prescribed ratio,
- wherein first and second clock signals are supplied respectively to the first and second input terminals of said timing averaging circuit, and a clock signal having a time difference obtained by internally dividing a time difference between pulses of the first and second signals is generated.
A clock control method for reducing jitter, comprising the steps of:
- providing a timing averaging circuit which generates, and outputs from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively from first and second input terminals, at a prescribed ratio;
- inputting first and second clock signals having a time difference between them to said timing averaging circuit;
- and
- generating a clock signal having a time difference obtained by internally dividing a time difference between pulses of the first and second clock signals to reduce jitter.
1 more element
A clock control circuit comprising:
- a timing averaging circuit which includes at least one timing dividing circuit that generates, and outputs from an output terminal, a signal which undergoes a transition after a delay equivalent to a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively to first and second input terminals, at a prescribed ratio, said delay being in response to rising and/or falling edge of the first and/or second signal;
- and
- a stage of dividing an entered clock into first and second clock signals and applying the first and second clock signals to said timing averaging circuit.
A clock control circuit comprising:
- (a) a plurality of serially connected timing averaging circuits each having two parallel-connected timing dividing circuits, said timing dividing circuits generating, and outputting from an output terminal, a signal which undergoes a transition after a delay equivalent to a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively to first and second input terminals, wherein transition timing of the first or second signal, whichever is earlier, is used as a reference;
- (b) wherein first and second clock signals are input respectively to first and second input terminals of each of said timing dividing circuits that constitute a first stage of said timing averaging circuits;
- (c) wherein first and second output signals, which are output from the output terminals of each of said timing dividing circuited of a timing averaging circuit of a preceding stage, are input respectively to first and second input terminals of each of said timing dividing circuits that constitute a timing averaging circuit of a succeeding stage;
- and
- (d) wherein first and second output signals from the output terminals of each of the timing dividing circuits of a timing averaging circuit of a final stage are extracted.
2 more elements
A clock control circuit comprising:
- (a) a stage to which a plurality of clocks of mutually different phases are input, this stage generating a plurality of control signals corresponding to transition timing of one clock of the plurality of clocks and to phase differences between the clocks;
- (b) a switch group, whose switching is controlled by the control signals, of controlling charging and discharging of a capacitor;
- (c) a stage of converting terminal voltage of the capacitor to a logic signal and outputting the logic signal;
- (d) a stage of varying charging or discharging speed of the capacitor by shifting switching control timings of switches in said switch group;
- and
- (e) a timing dividing circuit that outputs a clock signal having a phase difference obtained by internally dividing the phase difference between the clocks.
3 more elements
A clock control circuit comprising:
- (a) at least one timing dividing circuit that generates a signal having a phase difference obtained by internally dividing a phase difference between a predetermined set of clock phases of multiphase clocks having mutually different phases, said timing dividing circuit being provided in a number equivalent to the number of clock phases;
- (b) a stage of generating a signal having a duration equivalent to the phase difference between a predetermined pair of outputs regarding outputs of the plurality of timing dividing circuits;
- and
- (c) a stage of generating a multiphase clock by combining two signals of a predetermined pair regarding these signals generated in a number equivalent to the number of clock phases.
1 more element
A clock control circuit comprising:
- (a) a plurality of serially connected timing averaging circuits each having two parallel-connected timing dividing circuits that generate, and output from an output terminal, a signal which undergoes a transition after a delay equivalent to a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively to first and second input terminals, wherein transition timing of the first or second signal, whichever is earlier, is used as a reference;
- (b) frequency divider circuit that frequency divides an entered clock signal to first and second clock signals and outputting the first and second clock signals;
- (c) wherein the first and second clock signals from said frequency divider circuit are input respectively to first and second input terminals of each of said parallel-connected timing dividing circuits that constitute a first stage of said timing averaging circuits;
- (d) wherein first and second output signals, which are output from the output terminals of each of said timing dividing circuits of a timing averaging circuit of a preceding stage, are input respectively to first and second input terminals of each of said timing dividing circuits that constitute a timing averaging circuit of a succeeding stage;
- and
- (e) a combining circuit, to which first and second output signals from the output terminals of each of the timing dividing circuits of a timing averaging circuit of a final stage are input, said combining circuit outputting these signals upon multiplexing the same.
3 more elements
A timing averaging circuit comprising:
- parallel-connected timing dividing circuits that generate, and output from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively to first and second input terminals, wherein transition timing of the first or second signal, whichever is earlier, is used as a reference.
A timing dividing circuit comprising:
- (a) first and second switch elements turned ON and OFF in response to transitions of first and second input signals input respectively from first and second input terminals,
- (a1) wherein one of the switch elements is turned ON in response to transition of one of the first and second input signals, whereby current flows through the ON switch element to charge a capacitor, and
- (a2) wherein both switch elements then are turned ON in response to transition of the second signal, whereby charging speed of the capacitor is varied;
- and
- (b) a stage of outputting terminal voltage of the capacitor as a logic signal;
- (c) wherein there is generated an output signal which undergoes a transition at a time difference obtained by internally dividing a time difference between the first and second input signals, transition time of the first or second input signal serving as a reference for the time difference.
3 more elements
A timing dividing circuit comprising:
- (a) at least first and second switch element groups that include first and second switch elements each turned ON and OFF by rising and falling edges of first and second input signals input respectively from first and second input terminals,
- (b) a stage of controlling switching sequence of the switch elements of the first group in dependence upon one of a rising edge and falling edge of the first and second input signals, to vary charging speed of the capacitor during a process of charging the capacitor,
- (c) a stage of controlling switching sequence of the switch elements of the second group in dependence upon the other one of the rising edge and falling edge of the first and second input signals, to vary discharging speed of the capacitor during a process of charging the capacitor;
- and
- (d) a stage of outputting terminal voltage of the capacitor as a logic signal;
- (e) wherein there is generated a signal which undergoes a transition at a time difference obtained by internally dividing a time difference between the first and second input signals, the first or second input signal serving as a reference for the time difference.
3 more elements
A clock control circuit comprising:
- (a) a fixed delay circuit that delays an input signal by a predetermined phase;
- and
- (b) a timing averaging circuit that generates, and outputs from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals;
- (c) wherein an entered clock signal is applied to said fixed delay circuit chain, the entered clock signal and an output of said fixed delay circuit chain are applied to said timing averaging circuit, and a clock is extracted from the output terminal of said timing averaging circuit.
1 more element
A clock control circuit of a semiconductor integratesd circuit device for generating an internal clock from an entered external clock, comprising:
- (a) a delay-locked loop adapted to vary delay of the input signal, and having at least a phase-difference sensing circuit, a charge pump, a loop filter and a voltage-controlled delay circuit, to which an output from said loop filter is input as a control voltage;
- (b) a timing averaging circuit generating a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between two signals that are input with a fixed time difference between them;
- (c) wherein an output of said voltage-controlled delay circuit is supplied as an internal clock via a clock driver;
- and
- (d) wherein a clock signal, which is input to said phase-difference sensing circuit, obtained by inputting the external clock via an input buffer, and a signal obtained by passing said internal clock through an input buffer dummy circuit having a delay time equivalent to that of said input buffer are applied to said timing averaging circuit, with an output of said timing averaging circuit being applied as an input signal to said voltage-controlled delay circuit.
2 more elements
A delay-locked loop circuit comprising:
- (a) at least a phase-difference sensing circuit, a charge pump, a loop filter and a voltage-controlled delay circuit, to which an output from said loop filter is input as a control voltage, to vary delay of the input signal;
- and
- (b) a timing averaging circuit generating a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between two signals that are input with a fixed time difference between them;
- (c) wherein said timing averaging circuit is supplied with an input clock signal entering said phase-difference sensing circuit and an output signal from said voltage-controlled delay circuit, an output of said timing averaging circuit being applied as an input signal to said voltage-controlled delay circuit.
1 more element
A clock control circuit of a semiconductor integrated circuit device for generating an internal clock from an entered external clock, comprising:
- (a) a phase synchronizing loop circuit having at least a phase-difference sensing circuit, a charge pump, a loop filter and a voltage-controlled oscillator circuit;
- (b) a timing averaging circuit generating a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between two signals that are input with a fixed time difference between them;
- (c) wherein said timing averaging circuit is supplied with a clock signal, which is obtained by inputting the external clock via an input buffer, and a signal obtained by passing an internal clock, which is obtained by outputting a signal from said voltage-controlled oscillator via a clock driver, through an input buffer dummy circuit having a delay time equivalent to that of said input buffer;
- (d) a lock sensing circuit sensing a locked state from the output of said phase-difference sensing circuit;
- and
- (e) a changeover circuit supplying said phase-difference sensing circuit with either the input clock or the output of said timing averaging circuit;
- (f) wherein after locking is sensed, said changeover circuit changes over the signal supplied to said phase-difference sensing circuit from the input clock to a signal output from said timing averaging circuit.
4 more elements
A phase synchronizing loop circuit having at least a phase-difference sensing circuit, a charge pump, a loop filter and a voltage-controlled oscillator circuit, comprising:
- (a) a timing averaging circuit generating a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between two signals that are input with a fixed time difference between them;
- (b) wherein said timing averaging circuit is supplied with an input clock signal and an output signal from said voltage-controlled oscillator circuit, and an output of said timing averaging circuit is applied as one input of said phase-difference sensing circuit.
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- (c) a second delay circuit chain capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (d) a clock driver outputting an internal clock from an output of said second delay circuit chain;
- and
- (e) a timing averaging circuit, to which are input a clock signal from an input buffer and a signal obtained by passing an internal clock signal, which is output via said clock driver, through an input buffer dummy circuit having a delay time equivalent to that of said input buffer, to generate and output a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between these two signals;
- (f) wherein said first delay circuit chain is supplied with the output of said timing averaging circuit via a dummy delay circuit.
4 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- (c) a second delay circuit chain capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (d) a clock driver outputting an internal clock from an output of said second delay circuit;
- and
- (e) first and second timing averaging circuits, to which are input a clock signal from an input buffer and a signal obtained by passing an internal clock signal, which is output via said clock driver, through an input buffer dummy circuit having a delay time equivalent to that of said input buffer, to generate and output a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between these two signals, said first delay circuit chain being supplied with the output of said first timing averaging circuit via a dummy delay circuit;
- (f) wherein said first delay circuit chain is supplied with the output of said timing averaging circuit via a dummy delay circuit, and
- (g) wherein the output of said second timing averaging circuit is supplied as a control signal for controlling transfer of a signal from said first delay circuit chain to said second delay circuit chain.
5 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) two sets of delay circuit chains each of which includes:
- (b1) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time, and
- (b2) a second delay circuit chain capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit;
- and
- (c) first and second timing averaging circuits, to which are input a clock signal from an input buffer and a signal obtained by passing an internal clock signal, which is output via said clock driver, through an input buffer dummy circuit having a delay time equivalent to that of said input buffer, to generate and output a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between these two signals, said first delay circuit chain being supplied with the output of said first timing averaging circuit via a dummy delay circuit;
- (d) wherein said first delay circuit chain of each set is supplied with the output of said first timing averaging circuit via a dummy delay circuit,
- (e) wherein a frequency-divided signal obtained by frequency dividing the output of said second timing averaging circuit by a frequency divider circuit is supplied as a control signal for controlling transfer of a signal from said first delay circuit chain of each set to said second delay circuit, and
- (f) wherein an output from a changeover stage of alternately changing over between outputs of said second delay circuits of each of the sets is supplied to a clock driver and output from said clock driver as an internal clock.
6 more elements
The control circuit according to claim29, wherein said dummy delay circuit comprises an input buffer dummy and a clock driver dummy circuit.
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising
- (a) a synchronous delay circuit chain which includes:
- (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- (c) a second delay circuit chain capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (d) a monitor signal generating circuit for outputting a monitor signal for a period of time over which a clock pulse travels through an input buffer dummy circuit, which is equivalent to an input buffer to which the external clock is input, and a clock driver;
- and
- (e) a timing averaging circuit, to which are input a clock signal from said input buffer and a signal obtained by passing an internal clock signal, which is output via said clock driver, through said input buffer dummy circuit, to generate a signal having a time difference obtained by internally dividing a time difference between these two signals, and outputting this signal to said first delay circuit chain;
- (f) wherein travel of said pulse or pulse edge is halted in said first delay circuit chain while the monitor signal is being output.
4 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- (c) a second delay circuit chain, to which a signal from said first delay circuit chain is input, capable of passing a pulse or pulse edge along a length thereof proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (d) a monitor signal generating circuit outputting a monitor signal for a period of time over which a clock pulse travels through an input buffer dummy, which is equivalent to an input buffer, and a clock driver;
- (e) first and second timing averaging circuits, to which are input a clock signal from said input buffer and an output from said input buffer dummy obtained by passage therethrough of an internal clock signal output via the clock driver, for generating a signal having a time difference obtained by internally dividing a time difference between these signals, and outputting this signal to said first delay circuit chain;
- (f) wherein said first delay circuit chain of each set is supplied with the output of said first timing averaging circuit,
- (g) wherein the output of said second timing averaging circuit is used as a signal for controlling transfer of a clock signal from said first delay circuit chain to said second delay circuit chain, and
- (h) wherein travel of said pulse or pulse edge is halted in said first delay circuit chain while the monitor signal is being output;
- and
- (i) a changeover circuit changing over between the output of said second delay circuit and the output of said input buffer, to supply the output to said clock driver.
7 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) two sets of delay circuits each of which includes:
- (b1) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time, and
- (b2) a second delay circuit chain, to which a signal from said first delay circuit chain is input, capable of passing a pulse or pulse edge along a length thereof proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (c) first and second timing averaging circuits, to which are input a clock signal from an input buffer and a signal obtained by passing an internal clock signal, which is output via said clock driver, through an input buffer dummy circuit having a delay time equivalent to that of said input buffer, to generate and output a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between these two signals, said first delay circuit being supplied with the output of said first timing averaging circuit via a dummy delay circuit;
- (d) a frequency divider circuit frequency dividing outputs from said first and second timing averaging circuits;
- (e) wherein signals obtained by frequency dividing the outputs of said first and second timing averaging circuits by said frequency divider circuit are used as signals for controlling transfer of a clock signal from the first delay circuit chain of each set to said second delay circuit chain;
- (f) a first changeover circuit alternately changing over between outputs of said second delay circuits of each of the sets every clock cycle;
- and
- (g) a second changeover circuit for selecting the output of said input buffer or the output of said first changeover circuit, to supply the output to said clock driver.
7 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- (c) a second delay circuit chain, to which a signal from said first delay circuit chain is input, capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (d) a monitor signal generating circuit outputting a monitor signal for a period of time over which a clock pulse travels through an input buffer dummy, which is equivalent to an input buffer, and a clock driver;
- (e) first and second timing averaging circuits, to which are input a clock signal from said input buffer and a signal obtained by passing an internal clock signal, which is output via the clock driver, through said input buffer dummy circuit, to generate a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between these two signals, and to output this signal to said first delay circuit chain;
- (f) a first changeover circuit selecting the output of said input buffer or the output of said first timing averaging circuit, to supply the output to said first delay circuit chain;
- and
- (g) a second changeover circuit changing-over between the output of said first changeover circuit and the output of said second delay circuit chain;
- (h) wherein the output of said second timing averaging circuit and the output of said second changeover circuit are connected to said monitor signal generating circuit, and travel of said pulse or pulse edge is halted in said first delay circuit while the monitor signal is being output.
6 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- (c) a second delay circuit chain, to which a signal from said first delay circuit chain is input, capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (d) a monitor signal generating circuit outputting a monitor signal for a period of time over which a clock pulse travels through an input buffer dummy, which is equivalent to an input buffer, and a clock driver;
- (e) first, second and third timing averaging circuits, to which are input a clock signal from said input buffer and a signal obtained by passing an internal clock signal, which is output via the clock driver, through said input buffer dummy circuit, to output a signal having a time difference obtained by internally dividing a time difference between these two signals;
- (f) wherein the output of said first timing averaging circuit is input to said first delay circuit chain;
- (g) wherein the output of said second timing averaging circuit is used as a signal for controlling transfer of a clock signal from said first delay circuit chain to said second delay circuit chain;
- and
- (h) wherein the output of said third timing averaging circuit is connected to said monitor signal generating circuit;
- and
- (i) a changeover circuit changing-over between the output of said second delay circuit and the output of said input buffer;
- (j) wherein travel of said pulse or pulse edge is halted in said first delay circuit chain while the monitor signal is being output.
9 more elements
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:
- (a) a synchronous delay circuit which includes:
- (b) two sets of delay circuit chains each of which includes:
- (b1) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time, and
- (b2) a second delay circuit chains capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain;
- (c) the delay circuit chains of each of the sets including a timing averaging circuit, to which two inputs are applied, internally dividing, at a prescribed ratio, a time difference between these two input signals;
- (d) a monitor signal generating circuit for outputting a monitor signal for a period of time over which a clock pulse travels through an input buffer dummy, which is equivalent to an input buffer, and a clock driver;
- (e) the output of said input buffer being input to a frequency divider circuit;
- (f) the output of said input buffer being delivered as an internal clock via a first changeover circuit and being input to a second frequency divider and said monitor signal generating circuit via said input buffer dummy;
- (g) the frequency-divided output of said frequency divider circuit being supplied to said first delay circuit chain of each of the sets and being supplied as a signal for controlling transfer from said first delay circuit chain of each set to said second delay circuit chain;
- and
- (h) a second changeover circuit changing-over between outputs from the second delay circuit chains of each set;
- (i) wherein the output of said changeover circuit and the output of said input buffer are supplied to said first changeover circuit.
9 more elements
A synchronous delay circuit wherein an input clock signal is alternately driven by a PMOS transistor and an NMOS transistor in a delay circuit element constructing a delay circuit chain.
A synchronous delay circuit comprising:
- (a) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time;
- and
- (b) a second delay circuit chain for passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain, said pulse or pulse edge being passed through said second delay circuit chain from a stage corresponding to a position traveled by a signal through said first delay circuit chain;
- (c) wherein said first and second delay circuit chains have a timing averaging circuit outputting a signal having a time difference obtained by internally dividing a time difference between two input signals.
1 more element
A synchronous delay circuit
- (a) wherein a first delay circuit chain through which a signal is caused to travel for a fixed period of time has first and second switch elements serving as charging switches, provided in a delay circuit chain of one stage, turned ON by falling edges of first and second input signals, and said first and second switch elements are turned ON successively in response to the rising edges of the first and second input signals, whereby a common output node of said first and second switch elements is charged from a power supply side;
- (b) wherein said common connection mode is input to first and second switch elements, serving as discharging switches, of the next stage, said first and second switch elements of the next stage being turned ON in response to a rising edge of said common connection mode, whereby this output node is discharged to ground;
- (c) wherein a second delay circuit chain through which a signal propagates in a direction opposite that through which a signal travels through said first delay circuit chain has a charging switch and a discharging switch corresponding to each stage of the charging switch and discharging switch of said first delay circuit chain;
- and
- (d) wherein an output node of the charging switch of each stage of said first delay circuit chain is connected to an output node of the discharging switch of a preceding stage of a charging switch corresponding to said stage in said second delay circuit chain.
2 more elements
Dependencies are inferred from the claim text.