Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

A logic circuit comprising:

• an output stage control transistor means having a drain;
• and
• a first n-channel MOS field-effect transistor having a drain connected to said drain of said output stage control transistor means,
• said first input signal and the inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said first n-channel MOS field-effect transistor,
• the drains of said output stage control transistor means and said first n-channel MOS field-effect transistor being connected as said common node connected to an output stage.

A logic circuit comprising:

• two bipolar transistors having bases respectively receiving an inverse signal inverse to a first input signal and an inverse signal inverse to a second input signal;
• and
• an n-channel MOS field-effect transistor having a drain connected to a common node of emitters of said two bipolar transistors,
• said first input signal and said inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said n-channel MOS field-effect transistor,
• said emitters of said two bipolar transistors and the drain of said n-channel MOS field-effect transistor being connected as a common node to an output terminal.

A logic circuit comprising:

• two parallel n-channel MOS field-effect transistors having gates respectively receiving a first input signal and a second input signal;
• and
• a first n-channel MOS field-effect transistor having a drain connected to a common node of the drains of said n-channel MOS field-effect transistors,
• said first input signal and the inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said first p-channel MOS field-effect transistor,
• the drains of said n-channel MOS field-effect transistors and said first p-channel MOS field-effect transistor being connected as a common node connected to an output stage.

A logic circuit comprising:

• an n-channel MOS field-effect transistor having a gate receiving a first input signal and a source and a drain respectively receiving an inverse signal inverse to a second input signal being inputted to the source and the drain, respectively;
• and
• an output stage control transistor means having a drain connected to the drain of said n-channel MOS field-effect transistor,
• said common node of drains of said n-channel MOS field-effect transistor and said output stage control transistor means being coupled to an inverter having a CMOS transistor structure for outputting an output signal.

A semiconductor integrated circuit comprising a decoder circuit provided on a chip, said decoder circuit having an array of a plurality of logic circuits performing a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals, each of said logic circuits comprising:

• at least a first transistor for supplying charge through an output terminal to said external load;
• and
• at least a second transistor for pulling out the charge from said load through said output terminal,
• one of said first and second transistors being constituted by a MOS field-effect transistor having a drain connected to said output terminal,
• said MOS field-effect transistor having a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal to a gate of said MOS field-effect transistor,
• said MOS field-effect transistor being arranged such that the adjacent ones of said logic circuits share a source diffusion layer.