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US 2001/0040467 A1Published application
Method and apparatus for reducing soft errors in dynamic circuits
AssigneeIntel Corporation
InventorsSudarshan Kumar, Wenjie Jiang
Life of this patent
Estimating the term…
Abstract
A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
Claims19
A dynamic circuit comprising:
- a dynamic logic gate having an output node at which a logical output value of the logic gate is detected;
- and
- a keeper circuit coupled to the output node, the keeper circuit being configured to harden the dynamic circuit by increasing the critical charge at the output node.
A circuit comprising:
- a dynamic logic gate having an output node at which a logical output value of the dynamic logic gate is detected;
- a keeper circuit coupled to the output node, the keeper circuit including a feedback node;
- and
- a hardening capacitor coupled to the feedback node, the hardening capacitor to harden the circuit against soft errors.
1 more element
A method for reducing soft errors in a dynamic circuit, the method comprising:
- configuring a keeper circuit of the dynamic circuit to increase the critical charge at an output node of the circuit.
A method comprising:
- using a hardening capacitor coupled to a feedback node of a keeper circuit in a dynamic circuit to harden the dynamic circuit against soft errors.
Dependencies are inferred from the claim text.