US 2001/0040295 A1 · METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25 MICRON AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES PRIOR TO ILD DEPOSITION AND SEMICONDUCTOR CHIP MADE THEREBY

Abstract

A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.

Claims17

Dependent claims

A method for making a semiconductor chip having electrically conductive lines, comprising:

providing at least one substrate;
establishing at least one predetermined pattern of electrically conductive lines on the substrate;
annealing the electrically conductive lines;
then
depositing an inter-layer dielectric (ILD) between the lines.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/128,057Filed 29 Jul 1998

Published

15 Nov 2001

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/049
By introducing additional elements therein: by diffusing alloying elements
H10W 20/032
Of conductive parts of the interconnections: of conductive barrier, adhesion or liner layers
H10W 20/038
Of conductive barrier, adhesion or liner layers: covering conductive structures
H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material

Method for reducing stress-induced voids for 0.25 micron and smaller semiconductor chip technology by annealing interconnect lines prior to ild deposition and semiconductor chip made thereby

Life of this patent

Method for reducing stress-induced voids for 0.25 micron and smaller semiconductor chip technology by annealing interconnect lines prior to ild deposition and semiconductor chip made thereby

Life of this patent

Abstract

Claims17