Multi-chip memory apparatus and associated method

in a multi-chip integrated circuit having a memory chip, the memory chip including a memory-chip face surface, an improvement of a logic chip to which the memory chip is mountable, the logic chip having a logic-chip face surface, said logic chip comprising:

• logic circuitry for performing a logical function, said logic circuitry including components extending to the logic-chip face surface;
• a selected number of logic-chip interconnector elements formed upon the logic-chip face surface;
• and
• a selected number of memory-chip interconnector elements formed upon the memory-chip face surface, said memory chip interconnectors corresponding in number with the memory-chip interconnector elements and positioned such that, when the memory chip is positioned to be mounted upon the logic chip, said logic-chip interconnector elements and said memory-chip interconnector elements are aligned with one another, together to form an electrical interface between the memory chip and said logic circuitry which bonds said memory chip directly onto said logic circuitry, the electrical interface formed thereby of electrical characteristics appearing, to said logic circuitry, to substantially correspond to an internal node of said logic circuitry.

An integrated circuit comprising:

• a memory chip, said memory chip having a selected number of storage locations for storing data therein, said memory chip Including a memory-chip face surface;
• a logic chip having a logic-chip face surface positioned to abut together with the memory-chip face surface;
• and
• an interconnector forming interface positioned between said memory chip and said logic chip, said interconnector for electrically connecting said memory chip together with said logic chip which directly bonds said memory chip and said logic chip theretogether, the interface formed by said interconnector appearing to said memory chip to be of electrical characteristics substantially corresponding to an internal node of said memory chip.

A method for fabricating an integrated circuit, said method comprising the steps of:

• providing a memory chip having a selected number of storage locations for storing data therein, the memory chip including a memory-chip face surface;
• providing a logic chip having logic circuitry for performing a logic function, the logic chip including a logic-chip face surface;
• forming an interconnector upon at least one of the memory-chip face surface and the logic-chip face surface;
• connecting the memory chip and the logic chip by positioning the memory chip and the logic chip in abutting engagement by way of the interconnector formed during said step of forming.