Integrated circuit wiring and fabricating method thereof
AssigneeHyundai Electronics Industries Co., Ltd.
InventorPil-Sung Kim
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Abstract
The present invention relates to an integrated circuit wiring capable of reducing the contact resistance between lines and a fabricating method thereof. The wiring in accordance with the present invention includes a gate oxide film formed on the upper surface of a semiconductor device. A first line including a first silicon film pattern that is formed on an upper surface of the gate oxide film and has a certain width; and a silicide film pattern that is formed on the upper surface of the first silicon film and has a smaller width than that of the first silicon film pattern to thereby expose a certain region of the first silicon film pattern. A second line is formed to contact the silicide film pattern and the exposed certain region of the silicon film pattern.
Claims19
An integrated circuit wiring, comprising:
- a word line including a first silicon film pattern and a first silicide film pattern formed on the first silicon film pattern;
- and
- a bit line being in contact with both the first silicon film pattern and the first silicide film pattern.
An integrated circuit wiring, comprising:
- a gate oxide film formed on an upper surface of a semiconductor substrate;
- a word line including a first silicon film pattern that is formed on an upper surface of the gate oxide film and has a certain width, and a first silicide film pattern that is formed on an upper surface of the first silicon film pattern, wherein the first silicide film pattern has a smaller width than the certain width, and thus exposes a certain region of the first silicon film pattern;
- and
- a bit line formed in contact with the exposed certain region of the first silicon film pattern.
A method of fabricating an integrated circuit wiring, comprising the steps of:
- forming a gate oxide film on an upper surface of a semiconductor substrate;
- forming a first silicon film pattern on an upper surface of the gate oxide film;
- forming a first silicide film pattern with a smaller width than that of the first silicon film pattern on an upper surface of the first silicon film pattern;
- and
- forming a bit line on the upper surface of the first silicon film pattern and an upper surface of the first silicide film pattern.
A method of fabricating an integrated circuit wiring, comprising the steps of:
- forming a gate oxide film on an upper surface of a semiconductor substrate;
- forming a first silicon film on an upper surface of the gate oxide film;
- forming a first silicide film on an upper surface of the first silicon film;
- forming a first silicide film pattern and a first silicon film pattern with a greater width than that of the first silicide film pattern by sequentially patterning the first silicide film and the first silicon film.
- performing reoxidation;
- forming an interlayer insulator film;
- forming a contact hole exposing the first silicon film pattern and the first silicide film pattern by patterning the interlayer insulator film;
- and
- forming a bit line on an upper surface of the interlayer insulator film and in the contact hole.
Dependencies are inferred from the claim text.