Input replicator for interrupts in a simultaneous and redundantly threaded processor

A method of replicating interrupts to redundant threads, comprising:

• executing instructions in a leading thread and a trailing thread;
• tracking a difference between the leading and trailing thread in number of instructions committed;
• and
• interrupting the threads when an external interrupt is received, wherein said interrupting includes:
• stalling the leading thread until the counter indicates that the threads are synchronized;
• and
• initiating an interrupt service in each of the threads.

A processor, comprising:

• instruction execution circuitry that executes instructions in a leading thread and a redundant, trailing thread;
• an instruction counter that tracks a difference between the leading and trailing thread in number of instructions committed by the instruction execution circuitry;
• an interrupt counter that, when initiated, decrements from an initial value to zero;
• and
• instruction fetch circuitry coupled to the instruction execution circuitry to provide the instructions in the threads, wherein when the processor receives an external interrupt signal, the instruction fetch circuitry initiates the interrupt counter with the instruction counter value, immediately initiates an interrupt service routine in the leading thread, and initiates an interrupt service routine in the trailing thread when the interrupt counter reaches zero.

A method of replicating interrupts to redundant threads, comprising:

• executing instructions in a leading thread and a trailing thread;
• tracking a difference between the leading and trailing thread in number of instructions committed;
• and
• interrupting the threads when an external interrupt is received, wherein said interrupting includes:
• copying the difference to a counter;
• initiating an interrupt service routine in the leading thread without delay;
• decrementing the counter each time an instruction is committed in the trailing thread;
• and
• initiating an interrupt service routine in the trailing thread when the counter reaches zero.

A processor, comprising:

• instruction execution circuitry that executes instructions in a first thread and a redundant, second thread;
• a first instruction counter that counts instructions in the first thread committed by the instruction execution circuitry;
• a second instruction counter that counts instructions in the second thread committed by the instruction execution circuitry;
• a interrupt queue;
• and
• instruction fetch circuitry coupled to the instruction execution circuitry to provide the instructions in the threads, wherein when the processor receives an external interrupt signal, the instruction fetch circuitry determines which of the first and second threads is a leading thread, copies a value from a corresponding instruction counter to the interrupt queue, and initiates without delay an interrupt service routine in the leading thread, and initiates an interrupt service routine in the non-leading thread when the other instruction counter matches the value in the interrupt queue.

A method of replicating interrupts to redundant threads, comprising:

• executing instructions in a first thread and a second thread;
• counting a first number of instructions committed by a first thread;
• counting a second number of instructions committed by a second thread;
• and
• interrupting the threads when an external interrupt is received, wherein said interrupting includes:
• determining which of the first and second threads is a leading thread;
• copying a number of instructions committed by the leading thread to a queue;
• initiating an interrupt service routine in the leading thread without delay;
• and
• initiating an interrupt service routine in the non-leading thread when the number of instructions committed by the non-leading thread matches the number in the queue.

A processor, comprising:

• instruction execution circuitry that executes instructions in a leading thread and a redundant, trailing thread;
• a counter that tracks a difference between leading and trailing thread in number of non-speculative instructions provided to the instruction execution circuitry;
• and
• instruction fetch circuitry coupled to the instruction execution circuitry to provide the instructions in the redundant threads, wherein when the processor receives an external interrupt signal, the instruction fetch circuitry stalls the leading thread until the counter indicates that the threads are synchronized before initiating an interrupt service routine in each of the threads.

A computer, comprising:

• a simultaneously and redundantly threaded (“SRT”) processor;
• an main system memory coupled to said processor;
• an I/O controller coupled to said processor, wherein the I/O controller includes an interrupt controller that provides a processor interrupt to the processor;
• an I/O device coupled to said I/O controller, and configured to assert a device interrupt signal to the interrupt controller, wherein the interrupt controller asserts the processor interrupt signal if the device interrupt signal is unmasked,
• wherein the processor includes:
• instruction execution circuitry that executes instructions in a leading thread and a redundant, trailing thread;
• a counter that tracks a difference between the leading and trailing thread in number of instructions committed by the instruction execution circuitry;
• and
• instruction fetch circuitry coupled to the instruction execution circuitry to provide the instructions in the redundant threads, wherein when the processor detects an assertion of the processor interrupt signal, the instruction fetch circuitry stalls the leading thread until the counter indicates that the threads are synchronized before initiating an interrupt service routine in each of the threads.