Simultaneous and redundantly threaded processor branch outcome queue

A pipelined, simultaneous and redundantly threaded (“SRT”) processor, comprising:

• a fetch unit that fetches instructions from a plurality of threads of instructions;
• a program counter configured to assign program counter values to instructions in each thread that are fetched by the fetch unit;
• an instruction cache coupled to said fetch unit for storing instructions to be decoded and executed;
• and
• decode logic coupled to said instruction cache to decode the type of instructions stored in said instruction cache;
• wherein said processor is configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein misspeculation caused by incorrectly predicting the outcomes of branch instructions in a second program thread is avoided by using the actual outcomes of branch instructions in a first program thread to correctly determine the outcome of branch instructions in the second program thread.

A method of predicting branch instructions in an SRT processor which can fetch and execute a set of instructions in two separate threads so that each thread includes substantially the same instructions as the other thread, one of said threads being a leading thread and the other of said threads being a trailing thread, the method comprising:

• training a branch predictor to store predicted outcomes from branch instructions in the leading thread;
• probing the branch predictor to predict outcomes of future executions of branch instructions in the leading thread;
• storing actual outcomes of branch instructions in the leading thread in a branch outcome queue;
• probing the branch outcome queue to predict outcomes of corresponding branch instructions in the trailing thread.