US 2001/0037446 A1 · Processor and branch prediction method

Abstract

A next address computing section contains a selector and is connected to an instruction cache. The instruction cache maintains a predecode result of a branch instruction or predefined settings for a field in this branch instruction. Based on this information maintained in the instruction cache, the selector determines whether the compiler performed a branch prediction about the branch instruction or could not perform that branch prediction. When the compiler could not perform the branch prediction, the selector selects an output from a conditional branch prediction device (saturation counter section). When the compiler performed the branch prediction, the selector selects a prediction result by the compiler for a prediction in Agree mode. These selection results are used for setting a value of a register holding the next address. Based on this next-address register value, an instruction is fetched from the cache then inserted into a pipeline.

Claims16

Dependent claims

A processor comprising:

an instruction cache configured to fetch a first instruction from a program stored in a memory;
a decoding section, connected to the instruction cache, configured to decode the first instruction fetched in the cache;
an executing section, connected to the decoding section, configured to execute the decoded first instruction;
and
an address computing section, connected between the instruction cache and the execute section, configured to compute an address of a second instruction to be fetched into the instruction cache when the decoded first instruction is a branch instruction, the address computing section including:
a section configured to detect a result of a former branch prediction of the first instruction;
a section configured to compute the address according to the result of the former branch prediction unless the result represents an impossibility of prediction;
a section configured to confirm a successful prediction by comparing the result of the former branch prediction with a branch condition result ascertained from an execution of the first instruction;
and
a register in which the computed address is set when the successful prediction is confirmed.

7 more elements

Dependencies are inferred from the claim text.

Processor and branch prediction method

Life of this patent

Processor and branch prediction method

Life of this patent

Abstract

Claims16