Cycle count replication in a simultaneous and redundantly threaded processor

A pipelined, simultaneous and redundantly threaded (“SRT”) processor, comprising:

• a program counter configured to assign program count identifiers to instructions in each thread that are fetched by the processor;
• a register update unit configured to store a queue of instructions prior to execution by the processor;
• floating point execution units configured to execute floating point instructions;
• integer execution units configured to execute integer-based instructions;
• load/store units configured to perform load and store operations to or from data locations such as a data cache and data registers;
• and
• a cycle counter configured to keep a running count of processor clock cycles;
• wherein said processor is configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein false errors caused by incorrectly replicating cycle count values in the redundant program threads are avoided by using the actual values from cycle count reads in a first program thread for a second program thread.

A method of replicating cycle counter values in an SRT processor which can fetch and execute a set of instructions in two separate threads so that each thread includes substantially the same instructions as the other thread, one of said threads being a leading thread and the other of said threads being a trailing thread, the method comprising:

• stalling execution of the leading thread when a read cycle count (“RCC”) command is encountered in the leading thread;
• executing instructions in the trailing thread until the corresponding RCC command is encountered in the leading thread;
• and
• fetching a single copy of the cycle count value from the cycle counter and distributing said value to both threads.