US 2001/0037443 A1 · Logical pipeline for data communications system

Abstract

A new type of pipeline, generally referred to as a logical pipeline is disclosed. A logical pipeline generaly includes a set of hardware based pipeline stages that exchange data through a common pipeline memory, instead of only through intermediate fixed physical buffers. Thus, operational data is retrieved and stored by each stage using a single memory, and this permits flexible and programmable forms of pipelines that can be adapted as needed in response to a desired computation task. A common pipeline clock initiates processing of the data. Another variation is disclosed in the form of a logical “hybrid” pipeline, consisting of both software and hardware based pipeline stages, that are used to perform a set of computations in an interleaved fashion. In this manner, a data item can be handled first by a hardware pipeline stage, followed immediately by a software pipeline stage, etc. Furthermore, in a communications system, this arrangement permits processing for a number of ports to be distributed so that at any pipeline clock period, both hardware and software stages can be operating on different ports, or different communication tasks (i.e., transmit and receive).

Claims45

Dependent claims

A logical hybrid pipeline comprising:

a first set of hardware based pipeline stages;
and
a second set of software based pipeline stages coupled to said first set of hardware based pipeline stages;
and
a common pipeline clock used to initiate processing of data by both said first set of hardware based pipeline stages and said second set of software based pipeline stages during a pipeline clock period;
a common pipeline memory for storing processing results from both said first set of hardware based pipeline stages and said second set of hardware set of pipeline stages;
wherein said processing of data occurs in an interleaved manner in the logical hybrid pipeline, such that processing results are exchanged between said first set of hardware based pipeline stages and said second set of hardware set of pipeline stages during said pipeline clock period through said common pipeline memory.

4 more elements

A logical hybrid processing pipeline comprising:

a first set of hardware based pipeline stages configured as one or more application specific integrated circuit (ASIC) logic circuits;
and
a second set of software based pipeline stages configured as one or more general purpose processors executing software and/or firmware instructions;
and
the logical hybrid processing pipeline being further configured such that each pipeline stage of said first set of hardware based pipeline stages and said second set of software based pipeline stages receives an associated input data object for such pipeline stage from a prior pipeline stage implemented in hardware or hardware, and then performs a processing operation on said associated input data object to generate an associated output data object for such pipeline stage;
and
a common pipeline clock used to initiate said processing operation for both said first set of hardware based pipeline stages and said second set of software based pipeline stages;
wherein a plurality of associated input data objects are processed in a plurality of processing operations within a pipeline time interval associated with said common pipeline clock to generate a plurality of associated output data objects;
and
a pipeline memory for storing some or all of said plurality of associated input data objects and said plurality of associated output data objects;
wherein said pipeline memory is configured in the processing pipeline such that said some or all of said plurality of associated input data objects and said plurality of associated output data objects can be exchanged between said first set of hardware based pipeline stages and said second set of software based pipeline stages to effectuate a logical pipeline, and without using individual fixed hardware based buffers between pipeline stages.

8 more elements

A method of operating a pipeline including the steps of:

configuring one or more application specific integrated circuit (ASIC) logic circuits to form a first set of hardware based pipeline stages;
and
configuring one or more general purpose processors executing software and/or firmware instructions to form a second set of software based pipeline stages;
and
interconnecting the pipeline such that each pipeline stage of said first set of hardware based pipeline stages and said second set of software based pipeline stages receives an associated input data object for such pipeline stage and performs a processing operation on said associated input data object to generate an associated output data object for such pipeline stage;
and
providing a common pipeline clock to initiate said processing operation for both said first set of hardware based pipeline stages and said second set of software based pipeline stages;
wherein a plurality of associated input data objects are processed in a plurality of processing operations within a pipeline time interval associated with said common pipeline clock to generate a plurality of associated output data objects;
and
providing a pipeline memory for storing some or all of said plurality of associated input data objects and said plurality of associated output data objects;
exchanging said some or all of said plurality of associated input data objects and said plurality of associated output data objects between said first set of hardware based pipeline stages and said second set of software based pipeline stages to effectuate a logical pipeline.

8 more elements

Dependencies are inferred from the claim text.

Logical pipeline for data communications system

Life of this patent

Logical pipeline for data communications system

Life of this patent

Abstract

Claims45