Data Driven type information processing apparatus
AssigneeSharp Kabushiki Kaisha
InventorsKazuya Arakawa, Motoki Takase, Tsuyoshi Muramatsu
Life of this patent
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Abstract
A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the “H” level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.
Claims8
A data driven type information processing apparatus, comprising:
- a self-synchronous transfer control circuit controlling transfer and operating processes of a data packet including at least a destination node number, a generation number, an instruction code and data, by a transfer request signal and a transfer acknowledge signal;
- a pipeline register controlled by said self-synchronous transfer control circuit, for storing said data packet;
- an input/output control circuit controlling whether said data packet is to be circulated inside or output externally;
- and
- a data packet erasing circuit erasing a data packet stored in at least one of said pipeline registers and outputting other data packets to the outside.
A data driven type information processing apparatus, comprising:
- a self-synchronous transfer control circuit controlling transfer and operating processes of a data packet including at least a destination node number, a generation number, an instruction code and data, by a transfer request signal and a transfer acknowledge signal;
- a pipeline register controlled by said self-synchronous transfer control circuit, for storing said data packet;
- an input/output control circuit controlling whether said data packet is to be circulated inside or output externally;
- a data packet erasing circuit including a master reset input adding a new host transfer flag to the data packet and erasing at least one data packet, for adding a new host transfer flag to said data packet and erasing said data packet in accordance with master reset information;
- a plurality of host transfer flag operating circuits overwriting a host transfer flag of other data packet in accordance with said master reset information;
- and
- a host transfer flag detecting circuit detecting said host transfer flag.
A data driven type information processing apparatus, comprising:
- a self-synchronous transfer control circuit controlling transfer and operating processes of a data packet including at least a destination node number, a generation number, an instruction code and data, by a transfer request signal and a transfer acknowledge signal;
- a pipeline register controlled by said self-synchronous transfer control circuit for storing said data packet;
- an input/output control circuit controlling whether said data packet is to be circulated inside or output externally;
- a data packet erasing circuit including a master reset input for adding a new host transfer flag to a data packet and erasing at least one data packet, for adding a new host transfer flag to said data packet and erasing said data packet in accordance with master reset information;
- a host transfer flag operating circuit storing said master reset information, and overwriting and outputting the host transfer flag of input other data packet;
- and
- a host transfer flag detecting circuit detecting said host transfer flag.
Dependencies are inferred from the claim text.