Apparatus for controlling data transfer between a bus and memory array and method for operating same

A method of using a dynamic random access memory (DRAM) array as a next level cache memory in a computer system having a central processing unit (CPU) and a first level cache memory coupled to a bus, the method comprising the steps of:

• connecting an input port of a data buffer memory to the DRAM array;
• connecting an output port of the data buffer memory to the bus;
• operating the output port of the data buffer memory in response to a first clock signal;
• operating the input port of the data buffer memory in response to a second clock signal;
• transmitting a plurality of data values from the DRAM array to the input port of the data buffer memory during each cycle of the second clock signal;
• and
• transmitting a single data value from the output port of the data buffer memory to the bus during each cycle of the first clock signal.

A method of using a dynamic random access memory (DRAM) array as a next level cache memory in a computer system having a central processing unit (CPU) and a first level cache memory coupled to a bus, the method comprising the steps of:

• connecting an input port of a data buffer memory to the bus;
• connecting an output port of the data buffer memory to the DRAM array;
• operating the input port of the data buffer memory in response to a first clock signal;
• operating the output port of the data buffer memory in response to a second clock signal;
• transmitting a single data value from the bus to the input port of the data buffer memory during each cycle of the first clock signal;
• and
• transmitting a plurality of data values from the output port of the data buffer memory to the DRAM array during each cycle of the second clock signal.

A method of controlling refresh and internal operations of a dynamic random access memory (DRAM) array used as a next level cache memory in a computer system which includes a central processing unit (CPU) having a first level cache memory and a system controller, the method comprising the steps of:

• transmitting a first signal from the CPU to the DRAM array to initiate a transaction requested by the CPU;
• transmitting a second signal from the system controller to the DRAM array to initiate a transaction requested by the controller;
• coupling a terminal of the DRAM array to the system controller;
• and
• providing a third signal to the terminal to implement a protocol to manage refresh and internal operations within the DRAM array.