Multiplier capable of multiplication of large multiplicands and parallel multiplications small multiplicands
AssigneeDSP Group Ltd.
InventorJohn Suk-Hyun Hong
Life of this patent
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Abstract
A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a multiplication of double-width operands. In alternative embodiments, the adder operates in the same clock cycle as the multipliers or in a following clock cycle. Operand selection logic selects pairs of either single-width multiplicands or single-width partial multiplicands depending on for single or double-width multiplies.
Claims12
A multiply unit comprising:
- a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier;
- an adder having input ports which are larger than output ports of the multipliers, wherein an output port of the first multiplier is coupled to least significant bits of an input port of the adder, output ports of the second and third multipliers are coupled to input ports of the adder but not least or most significant bits of the input ports, and an output port of the fourth multiplier is coupled to an input port of the adder but not the least significant bits of the input port;
- and
- an output circuit that provides output signals from the multipliers when the multiplier circuit operates in a first mode, and provides an output signal from the adder when the multiply unit operates in a second mode.
A multiply unit comprising:
- a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier;
- an adder coupled to the first, second, third, and fourth multipliers, wherein the first multiplier is connected so that a least significant bit output from the first multiplier corresponds to a least significant bit in the adder, the second and third multipliers are connected so that a least significant bit output from the second multiplier and a least significant bit output from the third multiplier correspond to a first bit that is more significant than the least significant bit of the adder, and the fourth multiplier is connected so that a least significant bit output from the fourth multiplier corresponds to a second bit that is more significant than the first bit in the adder;
- and
- an output circuit that provides output signals from the multipliers when the multiplier circuit operates in a first mode, and provides an output signal from the adder when the multiply unit operates in a second mode.
A method for operating a multiply unit containing a plurality of multipliers, comprising:
- operating the multipliers separately to generate a plurality of output product values when the multiply unit operates in a first mode;
- and
- combining product values from the multipliers to generate only a single output product value when the multiply unit operates in a second mode.
Dependencies are inferred from the claim text.