Wire bonding to copper
AssigneeAgere Systems Inc.
InventorsSailesh Chittipeddi, Sailesh Mansinh Merchant
Life of this patent
Estimating the term…
Abstract
The specification describes techniques for wire bonding gold wires to copper metallization in semiconductor integrated circuits. A barrier layer is formed on the copper, and an aluminum bonding pad is formed on the barrier layer. Gold wire is then thermocompression bonded to the aluminum pad.
Claims11
A method for the manufacture of semiconductor integrated circuits wherein the top interconnection level comprises copper, the method comprising:
- (a) depositing a barrier layer on selected portions of said top interconnection level, said barrier layer being of a material selected from the group consisting of Ta, TaN, Ti, TiN, and combinations thereof,
- (b) depositing an aluminum layer on said barrier layer, and
- (c) bonding a conductive wire interconnection to said aluminum layer.
A method for the manufacture of semiconductor integrated circuits comprising the steps of:
- (a) forming a copper interconnection layer on a semiconductor substrate,
- (b) depositing a dielectric layer on said copper interconnection layer,
- (c) forming a plurality of openings in said dielectric layer to leave exposed portions of said copper interconnection layer,
- (d) depositing a barrier layer on said dielectric layer and on said exposed portions of said copper interconnection layer,
- (e) depositing an aluminum layer on said barrier layer,
- (f) etching away selected portions of said barrier layer and said aluminum layer to leave a barrier layer pad and an aluminum layer pad on said exposed portion of second conductive interconnection layer,
- (g) thermocompression bonding a conductive wire to said aluminum pad.
A method for the manufacture of semiconductor integrated circuits comprising the steps of:
- (a) forming a first conductive interconnection layer on a semiconductor substrate, said first conductive interconnection layer having a first interconnection pattern,
- (b) depositing a first dielectric layer on said first conductive interconnection layer,
- (c) forming at least one interlevel opening in said first dielectric layer to expose a portion of said first conductive interconnection layer,
- (d) depositing a first barrier layer on said first dielectric layer, and into said interlevel opening,
- (e) electroplating a copper layer on said first barrier layer, said copper layer having a thickness sufficient to fill said interlevel opening,
- (f) removing portions of said first barrier layer and said copper layer, leaving a barrier layer and a copper plug filling said interlevel opening,
- (e) depositing a barrier layer on said first dielectric layer and on said copper plug,
- (f) depositing an aluminum layer on said barrier layer,
- (g) etching away selected portions of said barrier layer and said aluminum layer to leave a barrier layer pad and an aluminum layer pad on said copper plug, and
- (h) thermocompression bonding a conductive wire to said aluminum pad.
A method for the manufacture of semiconductor integrated circuits comprising the steps of:
- (a) forming a copper interconnection layer on a semiconductor substrate,
- (b) forming a barrier layer on selected portions of said copper interconnection layer,
- (c) forming an aluminum layer on said barrier layer,
- (d) depositing an insulating capping layer over said semiconductor substrate,
- (e) removing selected portions of said insulating capping layer to expose portions of said aluminum layer, and
- (f) thermocompression bonding a conductive wire to said aluminum pad.
Dependencies are inferred from the claim text.