Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing
AssigneeTexas Instruments Incorporated
InventorsMark S. Rodder, Mahalingam Nandakumar
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Abstract
A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).
Claims29
A method of fabricating a transistor, comprising the steps of:
- forming an implant blocking structure on a semiconductor body, said implant blocking structure at least covering an area adjacent where a gate electrode is to be formed;
- forming a first doped region of a first conductivity type in said semiconductor body adjacent said implant blocking structure;
- and
- angle implanting a pocket region of a second conductivity type in said semiconductor body at least partially under said implant blocking structure to form a pocket in said semiconductor body.
A method of fabricating a transistor, comprising the steps of:
- forming a gate electrode on a semiconductor body;
- forming a sidewall spacer on the vertical edges of said gate electrode, said sidewall spacer comprising a material having an implant range less than that of said semiconductor body;
- forming a drain extension region of a first conductivity type in said semiconductor body adjacent said sidewall spacer;
- and
- angle implanting a pocket region of a second conductivity type in said semiconductor body at least partially under said sidewall spacer to form a pocket in said semiconductor body.
A transistor comprising:
- a gate electrode over a semiconductor body;
- a first sidewall spacer adjacent said gate electrode, said first sidewall spacer comprising a material having an implant range less than that of said semiconductor body;
- a drain extension region of a first conductivity type located in said semiconductor body generally aligned to said first sidewall spacer;
- and
- a pocket region of a second conductivity type at least partially below said first sidewall spacer and having a peak concentration spaced from a surface of said semiconductor body.
A method of forming a transistor comprising the steps of:
- forming a gate structure on a semiconductor body, said gate structure comprising at least two layers, wherein one of said two layers comprises a material having an implant range less than that of the semiconductor body;
- forming a drain extension region of a first conductivity type in said semiconductor body adjacent said gate structure;
- angle implanting a dopant of a second conductivity type to form a pocket region in said semiconductor body, wherein said gate structure blocks dopant from reaching a portion of the surface of said semiconductor body under an edge of said gate structure;
- and
- forming a source/drain region adjacent said gate structure.
Dependencies are inferred from the claim text.