# US 2001/0036686 A1 · Methods of forming an integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2001/0036686 A1 - Document ID: US20010036686A1 - Status: Published application - Kind: A1 - Application number: 09/449,026 - Filed: 1999-11-24 - Published: 2001-11-01 - Earliest claimed: 1998-10-01 - Assignees: Micron Technology, Inc. - Inventors: JOSEPH M. BRAND - Web page: https://patentgrep.com/patent/US20010036686A1 ## CPC - B29C 45/14655: {connected to or mounted on a carrier, e.g. lead frame} - H10W 40/778: {in encapsulations} - H10W 70/461: {specially adapted for cooling} - H10W 74/016: {using moulds} - B29C 45/02: Transfer moulding, i.e. transferring the required volume of moulding material by a plunger from a "shot" cavity into a mould cavity - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - Y10S 257/905: Plural dram cells share common contact or common trench - B29C: SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING (making preforms B29B11/00; making laminated products by combining previously unconnected layers which become one product whose layers will remain together B32B37/00 - B32B41/00) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling. ## Claims ### Claim 1 An integrated circuit device comprising: a semiconductor die; a first housing encapsulating the semiconductor die; a heat sink positioned proximate to the first housing; and a second housing encapsulating at least a portion of the heat sink. ### Claim 2 (depends on 1) The integrated circuit device according to claim 1 further comprising at least one first lead coupled with the semiconductor die and the first housing encapsulates at least a portion of the at least one first lead. ### Claim 3 (depends on 1) The integrated circuit device according to claim 1 wherein the heat sink comprises: a body; and at least one second lead coupled with the body and the second housing encapsulates at least a portion of the at least one second lead. ### Claim 4 (depends on 3) The integrated circuit device according to claim 3 wherein the at least one second lead is configured to dissipate heat from the semiconductor die. ### Claim 5 (depends on 1) The integrated circuit device according to claim 1 wherein the second housing encapsulates a majority of the heat sink. ### Claim 6 (depends on 1) The integrated circuit device according to claim 1 wherein the second housing encapsulates a majority of the heat sink and at least a portion of the first housing. ### Claim 7 (depends on 1) The integrated circuit device according to claim 1 wherein the second housing encapsulates a majority of the heat sink and a majority of the first housing. ### Claim 8 (depends on 1) The integrated circuit device according to claim 1 wherein the semiconductor die comprises a synchronous-link dynamic random access memory device and the second housing forms one of a vertical surface mounted package and a horizontal surface mounted package. ### Claim 9 An integrated circuit device comprising: a semiconductor die having a plurality of bond pads; a plurality of leads electrically coupled with the bond pads of the semiconductor die; a first housing encapsulating the semiconductor die and at least a portion of the leads; a heat sink thermally coupled with the first housing; and a second housing encapsulating at least a portion of the heat sink. ### Claim 10 (depends on 9) The integrated circuit device according to claim 9 wherein the heat sink comprises a metal and the first housing contacts the metal. ### Claim 11 (depends on 9) The integrated circuit device according to claim 9 wherein the heat sink includes at least one lead configured to dissipate heat from the semiconductor die. ### Claim 12 (depends on 9) The integrated circuit device according to claim 9 wherein the second housing forms one of a vertical surface mounted package and a horizontal surface mounted package. ### Claim 13 (depends on 9) The integrated circuit device according to claim 9 wherein the second housing encapsulates the first housing. ### Claim 14 An integrated circuit device comprising: a first housing formed about a semiconductor die and at least portions of a plurality of leads electrically coupled with the semiconductor die; a heat sink thermally coupled with the first housing; and a second housing formed about the heat sink and at least a portion of the first housing. ### Claim 15 (depends on 14) The integrated circuit device according to claim 14 wherein the first housing and second housing individually comprise an encapsulant housing. ### Claim 16 (depends on 14) The integrated circuit device according to claim 14 wherein the heat sink contacts the first housing. ### Claim 17 (depends on 14) The integrated circuit device according to claim 14 wherein the heat sink further includes at least one lead configured to dissipate heat from the semiconductor die. ### Claim 18 A synchronous-link dynamic random access memory device comprising: a semiconductor die bearing synchronous-link dynamic random access memory circuitry and having a plurality of bond pads coupled therewith; a plurality of leads electrically coupled with the bond pads of the semiconductor die; a first housing encapsulating the semiconductor die and at least a portion of the leads; a heat sink positioned proximate the first housing and configured to draw heat from the semiconductor die; and a second housing encapsulating the heat sink and at least a portion of the first housing. ### Claim 19 (depends on 18) The synchronous-link dynamic random access memory device according to claim 18 wherein the second housing forms one of a vertical surface mounted package and a horizontal surface mounted package. ### Claim 20 (depends on 18) The synchronous-link dynamic random access memory device according to claim 18 wherein the heat sink comprises at least one lead configured to dissipate heat from the semiconductor die. ### Claim 21 A method of forming an integrated circuit device comprising: providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling. ### Claim 22 (depends on 21) The method according to claim 21 wherein the providing comprises providing a semiconductor die coupled with plural leads of a lead frame. ### Claim 23 (depends on 22) The method according to claim 22 further comprising bending the leads to form one of a vertical surface mounted package and a horizontal surface mounted package. ### Claim 24 (depends on 21) The method according to claim 21 wherein the forming the first housing and the forming the second housing individually comprise encapsulating. ### Claim 25 (depends on 21) The method according to claim 21 wherein the forming the second housing comprises encapsulating at least a portion of the first housing. ### Claim 26 (depends on 21) The method according to claim 21 further comprising providing the heat sink with at least one lead. ### Claim 27 A method of forming an integrated circuit device comprising: providing a semiconductor die having a plurality of bond pads; providing a first lead frame having a plurality of leads; providing a second lead frame having a heat sink; electrically coupling the bond pads of the semiconductor die with the leads of the first lead frame; first encapsulating the semiconductor die and at least a portion of the leads, the first encapsulating forming a first housing; thermally coupling the heat sink with the first housing; and second encapsulating at least a portion of the heat sink forming a second housing following the thermally coupling. ### Claim 28 (depends on 27) The method according to claim 27 wherein the second encapsulating further comprises encapsulating at least a portion of the first housing. ### Claim 29 (depends on 27) The method according to claim 27 wherein the second encapsulating further comprises encapsulating a majority of the heat sink and a majority of the first housing. ### Claim 30 (depends on 27) The method according to claim 27 wherein the thermally coupling comprises positioning the heat sink to contact the first housing. ### Claim 31 (depends on 27) The method according to claim 27 further comprising bending the leads to form one of a vertical surface mounted package and a horizontal surface mounted package. ### Claim 32 (depends on 27) The method according to claim 27 wherein the providing the second lead frame comprises providing the heat sink with at least one lead. ### Claim 33 A method of forming an integrated circuit device comprising: providing a semiconductor die electrically coupled with a plurality of leads; forming a first housing about the semiconductor die and at least a portion of the leads; providing a heat sink; and forming a second housing about at least a portion of the heat sink, the forming the second housing thermally coupling the heat sink with the semiconductor die. ### Claim 34 (depends on 33) The method according to claim 33 further comprising positioning a heat sink proximate the first housing prior to forming the second housing. ### Claim 35 (depends on 33) The method according to claim 33 wherein the forming the first housing and the forming the second housing individually comprise encapsulating. ### Claim 36 (depends on 33) The method according to claim 33 wherein the forming the second housing comprises forming the second housing about at least a portion of the first housing. ### Claim 37 (depends on 33) The method according to claim 33 wherein the forming the second housing comprises encapsulating at least a portion of the heat sink and at least a portion of the first housing. ### Claim 38 (depends on 33) The method according to claim 33 wherein the providing the heat sink comprises providing the heat sink having at least one lead. ### Claim 39 (depends on 33) The method according to claim 33 further comprising bending the leads to form one of a vertical surface mounted package and a horizontal surface mounted package. ### Claim 40 A method of forming a synchronous-link dynamic random access memory edge-mounted device comprising: providing a semiconductor die having a plurality of bond pads; providing a first lead frame having a plurality of leads; providing a second lead frame having a heat sink; electrically coupling the bond pads of the semiconductor die with the leads of the first lead frame; positioning the semiconductor die and the first lead frame within a first mold following the electrically coupling; first encapsulating the semiconductor die and at least a portion of the leads within the first mold using a first encapsulant; curing the first encapsulant forming a first housing; removing the first housing from the first lead frame; positioning the heat sink of the second lead frame to contact a surface of the first housing; providing the semiconductor die and the second lead frame within a second mold following the positioning the heat sink; second encapsulating the first housing and the heat sink within the second mold using a second encapsulant; curing the second encapsulant forming a second housing; removing the second housing from the second lead frame; trimming the leads; and bending the leads to form one of a vertical surface mounted package and a horizontal surface mounted package.