Device level layout optimization in electronic design automation

Abstract

According to a custom physical design process for integrated circuits, a method is provided for creating layouts characterized by optimal-length chains for different types of MOS circuit designs, including mixed-signal MOS designs. A chaining engine having a device library and operating on a computer converts a circuit representation such as a netlist file into a layout file characterized by optimal-length chains. Such conversion may be accomplished in linear time. From a circuit representation, a bipartite graph is prepared. A starting node in the bipartite graph is selected according to enumerated Euler trail algorithm rules. A constraint greedy walk is conducted to generate layout chains, and is preferably repeated until the bipartite graph is exhausted of edges, at which point the resulting layouts are returned. A single optimal layout solution can be obtained without enumerating all the possible layout options, resulting in a considerable speed advantage over conventional techniques. The disclosed chaining methods may be used, for example, in both customizing layouts and in creating automated layouts when enhanced with optional partitioning and/or folding capabilities.

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