Microcode scalable processor

A processing system comprising:

• a microcode sequencer;
• the microcode sequencer including a plurality of modules, each of the modules enabling a specific function;
• and
• a processor coupled to the microcode sequencer, the processor including a decode buffer for receiving instructions;
• and a decoder coupled to the decode buffer and the microcode sequencer for determining the type of instruction received by the decode buffer;
• the decoder for enabling a selection signal to select the specific function of the microcode sequencer based upon the type of instruction.

A processing system comprising:

• a microcode sequencer;
• the microcode sequencer including a plurality of modules, each of the modules enabling a specific function;
• the microcode sequencer including a microcode engine for receiving the selection signal and providing the specific function;
• a microcode decoder means for decoding the instructions;
• and a hardware mechanism for receiving the decoded instructions and for providing one of the specific functions;
• and
• a processor coupled to the microcode sequencer, the processor including a decode buffer for receiving instructions;
• and a decoder coupled to the decode buffer and the microcode sequencer for determing the type of instruction received by the decode buffer;
• the decoder for enabling a selection signal to select the specific function of the microcode sequencer based upon the type of instruction, the decoder including a multiplexer which is enabled by the selection signal and also receives a macro instruction that maps an entry address to a microcode engine within the microsequencer, wherein a bit within the decoder is set to enable the selection signal.