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AssigneeIntel Corporation
InventorsPatrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Bosewell, Karol F. Menezes
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A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
A method comprising the steps of:
A method for staggering execution of an instruction comprising the steps of:
A processor comprising:
A system for staggering execution of an instruction, comprising:
A circuit for executing instructions comprising:
Dependencies are inferred from the claim text.