Simultaneous and redundantly threaded processor store instruction comparator

A method of detecting transient faults in a simultaneously and redundantly threaded microprocessor having at least two threads, the method comprising:

• executing a program as a first thread;
• generating a first committed store request from said first thread;
• storing said first committed store request in a storage queue;
• executing the program as a second thread;
• generating a second committed store request from said second thread;
• storing said second committed store in said storage queue;
• checking an address and data associated with said first committed store request against an address and data associated with said second committed store request in a compare logic;
• and
• allowing one of said first and second committed store requests to execute if the checking step shows those committed store requests are exactly the same.

A simultaneous and redundantly threaded microprocessor comprising:

• a first pipeline executing a first program thread;
• a second pipeline executing a second program thread;
• a store queue coupled to each of said first and second pipelines;
• a compare circuit coupled to said store queue;
• wherein each of said first and second program threads independently generate corresponding committed write requests, and each thread places those committed write requests in the store queue;
• and
• wherein said compare circuit detects transient faults in operation of said first and second pipeline by comparing at least the committed store requests from each thread.

A pipelined, simultaneous and redundantly threaded (“SRT”) processor, comprising:

• a fetch unit that fetches instructions from a plurality of threads of instructions;
• an instruction cache coupled to said fetch unit and storing instructions to be decoded and executed;
• and
• decode logic coupled to said instruction cache to decode the type of instructions stored in said instruction cache;
• wherein said processor processes a set of instructions in a leading thread and also in a trailing thread, and wherein the instructions in the trailing thread are substantially identical to the instructions in the leading thread, the instructions in the trailing thread beginning processing through the processor after the corresponding instructions in the leading thread begin processing through the processor;
• and wherein said processor detects transient faults by verifying as between the leading and trailing threads only the committed stores and uncached memory read requests.

A method of detecting transient faults in a simultaneous and redundantly threaded microprocessor having at least two threads, the method comprising:

• executing a program as a first thread;
• generating a first committed store request from said first thread;
• storing said first committed store request in a storage queue;
• executing the program as a second thread;
• generating a second committed store request from said second thread;
• checking an address and data associated with said first committed store request against an address and data associated with said second committed store request;
• and
• allowing one of said first and second committed store requests to execute if the checking step shows those committed store requests are exactly the same.

A simultaneous and redundantly threaded microprocessor comprising:

• a first pipeline executing a first program thread;
• a second pipeline executing a second program thread;
• a store queue coupled to at least said first pipelines;
• wherein each of said first and second program threads independently generate corresponding committed write requests, at least said first thread places the committed write requests in the store queue;
• and
• wherein said second thread detects transient faults in operation of said first and second pipeline by comparing at least the committed store requests from each thread.