Multiple mode memory module

A memory control unit coupled during use to a system bus for receiving memory addresses therefrom, comprising:

• a plurality of memory units comprised of a plurality of semiconductor memory devices having a plurality of addressable memory storage locations;
• a second bus coupled between said memory control unit and said memory units, including separate first and second signal lines;
• said first signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units;
• and
• said second signal line for transmitting a signal asserted by one of said memory units selected by a transmitted memory unit select address, the asserted signal indicating an access speed of the selected memory unit, said second signal fine being different and separate from said first signal lines.

A memory unit adapted to be coupled to a memory control unit, comprising:

• a semiconductor memory device having a plurality of addressable memory storage locations;
• first signal ports adapted to be coupled to said memory control unit through first signal lines, said first signal ports disposed to receive, during a memory access cycle, from said memory control unit a memory address selecting said memory unit;
• a logic circuit disposed within said memory unit to receive said memory address through said first signal ports, generating a signal in response to said memory address, said asserted signal indicating an access speed of said selected memory unit;
• and
• a second signal ports adapted to be coupled to said memory control unit through a second signal line, said second signal ports coupled to said logic circuit and disposed to transmit said asserted signal to said memory control unit, said second signal port being different and separate from said first signal ports.

A process in a memory unit adapted to a control unit, comprising the steps of:

• providing said memory unit with a plurality of semiconductor memory devices having a plurality of addressable memory storage locations, first signal ports, and a second signal port;
• receiving from said control unit a memory address selecting said memory unit through said first ports;
• and
• asserting a signal indicating an access speed of said selected memory unit through said second port being different and separate from said first signal lines.

A proceed in a memory control unit coupled to a plurality of memory units, comprising the steps of:

• providing first signal lines coupled between said memory control unit and said memory units, a second signal line coupled between said memory control unit and said memory units and a being separate and different from said first signal lines, and said memory units each having a plurality of semiconductor memory devices having a plurality of addressable memory storage locations;
• transmitting a memory address selecting one of said memory units through said first signal lines;
• transmitting a signal asserted by one of said memory units selected by a transmitted memory unit address, said asserted signal indicating an access speed of said selected memory unit;
• and
• specifying a duration of said memory access cycle so as to make a duration of said memory access cycle compatible with the access speed of at least said semiconductor memory devices of said selected memory unit.