Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data

Interleaved data path and output management architecture for an interleaved memory, divided in at least a first bank and a second bank (EVEN BANK, ODD BANK), each provided with an array of sense amplifiers (EVEN SENSE, ODD SENSE) and a register of read data (DATA OD REGISTER, DATA EV REGISTER), and comprising an array of output buffers (BUFFOUT), controlled by external protocol signals (CE, OE) and a control and timing circuitry (TIMING) receiving as input external protocol signals (ALE, RD, CE) and producing enabling and/or path selection signals (SAEN_EVEN, SAEN_ODD, SAlatch_EVEN, SAlatch_ODD, LOAD_EVEN, LOAD_ODD), characterized in that further comprises

• at least a third register (DATA OUT REGISTER) to the inputs of which are fed the output data of said registers of data read from the two banks DATA EV REGISTER, DATA OD REGISTER) in function of path selection signals (LOAD_EVEN, LOAD_ODD) produced by said control and timing circuitry (TIMING);
• an array of pass-gates controlled in common by a control signal (DLATCHN) generated by said control and timing circuitry (TIMING) enabling the transfer of data stored in said third register (DATA OUT REGISTER) to respective inputs of said array of output buffers (BUFFOUT).