Method and apparatus for providing a memory with write enable information
AssigneeRambus Inc.
InventorsFrederick Abbott Ware, Craig Edward Hampel, Donald Charles Stark, Matthew Murdy Griffin
Life of this patent
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AssigneeRambus Inc.
InventorsFrederick Abbott Ware, Craig Edward Hampel, Donald Charles Stark, Matthew Murdy Griffin
Estimating the term…
A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.
A method for providing a memory with data and write enable signals, comprising the steps of:
A memory, comprising:
A method for receiving data and write enable bits for a memory, comprising the steps of:
A memory, comprising:
A method for receiving data and write enable information for a memory, comprising the steps of:
A computer system, comprising:
Dependencies are inferred from the claim text.