US 2001/0034808 A1 · CACHE MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM

Abstract

A highly associative cache memory device is arranged to use as a data memory a memory like a SDRAM to be accessed by a row access and a column access and locate the data of all the ways of the same set number on the same row. A cache control circuit 5 executes the row access to the data memory before fixing a cache hit determination. If a cache is hit, the column access is executed by the hit way number. If a cache-miss takes place and thus the write back is necessary, the column access is executed by using the replace way number. If a cache-miss takes place and thus no write back is necessary, the column access is interrupted. These operations make it possible to reduce an access latency and a busy time of a memory bank as saving the pins of an LSI being inputted with data if an outside SDRAM chip is used for the data memory. If the cache miss takes place, the row access is effective for reading the data to be written back to the cache. This prevents the using efficiency of the data memory bank from being lowered.

Claims12

Dependent claims

A cache memory device including a data memory for storing data and a tag memory for storing an address of stored data in the data memory, comprising:

said data memory including a memory element to be accessed by two steps of a row access and a column access;
and
said row access to said data memory being executed before determining whether the access hits or miss in the cache when doing a cache access.

An information processing system having a processor, a main storage unit, a cache memory device for holding part of data to be stored in said main storage unit, a processor bus for connecting said processor with said cache memory device, and a memory bus for connecting said main storage unit with said cache memory device, comprising:

said processor having means for requesting data to be loaded onto said cache memory in said main storage unit through said processor bus and means for requesting data in said processor to be stored in said cache memory device through said processor bus;
said main storage unit having means for sending data in response to a load request from said cache memory device to said cache memory device through said memory bus and means for storing data in response to a store request from said cache memory device through said memory bus;
said cache memory device including a data memory for storing data, a tag memory for storing an address, and means for controlling a cache, said data memory being including a memory element to be accessed by two steps of a row access and a column access, and said cache memory being set associative with plural blocks for the same set numbers for index address of said tag memory;
the data of all the blocks in the same set being located at the same row address of said data memory;
and
wherein said means for controlling the cache executes the row access of said data memory before fixing cache hit determination when doing the cache access,
executes the column access to said data memory with the block number that contains the accessed data if the access hits in the cache,
executes the column access to said data memory with the block number that is replaced if the access misses in the cache and it is necessary to write the data in the block to be replaced back to said main storage unit, and
cancels the column access to said data memory if it is unnecessary to write the data in the block to be replaced back to said main storage unit.

6 more elements

Dependencies are inferred from the claim text.

Cache memory device and information processing system

Life of this patent

Cache memory device and information processing system

Life of this patent

Abstract

Claims12