Interface, structure and method for transmitting data of PCI bus
AssigneeVIA Technologies, Inc.
InventorsSheng-Chang Peng, Chau-Chad Tsai, Hsuan-Yi Wang, Chi-Che Tsai
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Abstract
A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.
Claims22
A bus data interface that transmitting data on a PCI bus, comprising:
- a high-bit transmitting buffer, to buffer a high-bit data;
- a low-bit transmitting buffer, to buffer a low-bit data;
- a multiplexer, coupled to the high-bit transmitting buffer and the low-bit transmitting buffer and receiving an internal bus clock, wherein the multiplexer alternatively outputs the high-bit transmitting data or the low-bit transmitting data to the PCI bus in response to a high potential level and a low potential level of the internal bus clock;
- a strobe generator, to generate a data strobe signal in response to the internal bus clock when the bus data interface outputs data to the PCI bus;
- and
- a data distributor, coupled to the PCI bus, for receiving the high-bit receiving data and the low-bit receiving data from the PCI bus in repines to the data strobe signal;
- wherein the strobe generator uses either a bus grant signal pin or a bus request signal pin as an output pin to transmit the data strobe signal.
A bus structure to transmit data on a PCI bus, wherein the PCI bus comprises
- a bus grant signal and a bus request signal, the bus structure comprising:
- a transmission compatible apparatus, coupled to the PCI bus, further comprising:
- a high-bit transmitting buffer, to receive and temporarily store a high-bit transmitting data;
- a low-bit transmitting buffer, to receive and temporarily store a low-bit transmitting data;
- a multiplexer, coupled to the high-bit and low-bit transmitting buffers to receive a first internal bus clock signal, wherein the multiplexer alternatively outputs the high-bit transmitting data or the low-bit transmitting data to the PCI bus in response to a high potential level and a low potential level of the internal bus clock;
- and
- a strobe generator, for generating a data strobe signal according to the first internal bus clock signal when the transmission compatible apparatus is coupled to the PCI bus;
- a reception compatible apparatus, coupled to the PCI bus and comprising:
- a data distributor, coupled to the PCI bus and receiving data from the PCI bus and outputting a high-bit receiving data and a low-bit receiving data in response to the data strobe signal.
A method for transmitting data on a PCI bus, in a computer comprises a plurality of masters and a host bridge coupled to the PCI bus, said PCI bus having a plurality of bus request signals and a plurality of bus grant signals, the method comprising:
- detecting whether individual master supports a dual transmission mode while starting up the computer;
- and
- asserting the corresponding bus request signal of individual master supporting the dual transmission mode.
Dependencies are inferred from the claim text.