Packet transmission/reception processor
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsHirotaka Ito, Yoshihiro Tabira
Life of this patent
Estimating the term…
Abstract
If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.
Claims10
A packet transmission/reception processor coupled to a CPU, the processor comprising:
- a link core circuit for receiving a packet externally delivered through a bus;
- and
- a packet processing controller for processing the packet received by the link core circuit, making a packet to be transmitted in response to the received packet, and then supplying the packet to be transmitted to the link core circuit,
- wherein the link core circuit also sends out the packet to be transmitted, supplied from the packet processing controller, by way of the bus.
A packet transmission/reception processor coupled to a CPU, the processor comprising:
- a packet processing controller for making a packet to be transmitted;
- and
- a link core circuit for sending out the packet to be transmitted, which has been made by the controller, to an external unit by way of a bus and for receiving a packet delivered externally through the bus,
- wherein the controller processes the packet received by the link core circuit, and makes a packet to be transmitted in response to the received packet and supplies the packet to be transmitted to the link core circuit after having processed the received packet.
A packet transmission/reception processor coupled to a CPU, the processor comprising:
- a link core circuit for receiving a packet delivered externally through a bus;
- and
- a packet processing controller for making and supplying a request packet to the link core circuit, processing the packet received by the link core circuit, and making and supplying a next request packet consecutively to the link core circuit until a predetermined portion of the former request packet has been transferred,
- wherein the link core circuit transmits the packet, supplied from the controller, by way of the bus.
Dependencies are inferred from the claim text.