Capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors and DRAMs

An etching process, comprising:

• providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight);
• providing a second material over the first material;
• and
• etching the second material at a faster rate than the first material.

A method of forming an opening, comprising:

• forming an etch stop layer over a substrate, the etch stop layer comprising carbon;
• forming an insulative layer over the etch stop layer;
• and
• etching through the insulative layer utilizing conditions selective for etching the insulative layer at a faster rate than the etch stop layer to form an opening through the insulative layer to the etch stop layer.

A capacitor forming method, comprising:

• forming a wordline over a substrate, the wordline having a sidewall;
• forming an insulative spacer along the sidewall;
• forming an etch stop layer over the wordline and over the insulative spacer;
• at least one of the etch stop layer and the insulative spacer comprising carbon;
• forming an insulative layer over the etch stop layer;
• etching through the insulative layer to the etch stop layer to form an opening through the insulative layer;
• and
• forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening.

A capacitor forming method, comprising:

• forming a wordline over a substrate;
• defining a node proximate the wordline;
• forming an etch stop layer over the wordline, the etch stop layer comprising carbon;
• forming an insulative layer over the etch stop layer;
• etching through the insulative layer to the etch stop layer to form an opening through the insulative layer;
• and
• forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening.

A DRAM forming method comprising:

• forming a pair of wordlines over a substrate;
• defining three nodes proximate the wordlines, the three nodes comprising a first node, second node and third node;
• the second node being in gated electrical connection with the first node through one of the wordlines and being in gated electrical connection with the third node through the other of the wordlines;
• forming an etch stop proximate the wordlines, the etch stop comprising carbon;
• forming an insulative layer over the etch stop;
• forming first, second and third openings extending through the insulative layer, the forming the first second and third openings comprising etching through the insulative layer to the etch stop;
• forming a first capacitor construction in electrical connection with the first node;
• forming a second capacitor construction in electrical connection with the third node;
• and
• forming a bit line contact in electrical connection with the second node.

A capacitor construction, comprising:

• a storage node extending within an insulative layer, at least a portion of the storage node extending along and against a material that comprises carbon;
• a second electrode proximate the storage node;
• and
• a dielectric layer between the second electrode and the storage node.

A DRAM construction, comprising:

• a pair of wordlines over a substrate, the wordlines comprising sidewall edges;
• three nodes proximate the wordlines, the three nodes comprising a first node, second node and third node, the second node being in gated electrical connection with the first node through one of the wordlines and being in gated electrical connection with the third node through the other of the wordlines;
• a carbon-containing material proximate the wordlines;
• an insulative layer over the etch stop;
• a first capacitor construction in electrical connection with the first node, the first capacitor construction comprising a first storage node;
• a second capacitor construction in electrical connection with the third node, the second capacitor construction comprising a second storage node;
• and
• a bit line contact in electrical connection with the second node, at least one of the first storage node, second storage node and bit line contact being in physical contact with the carbon-containing material.