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US 2001/0034091 A1Published application
Methods of forming transistors
AssigneeMicron Technology, Inc.
InventorsCharles H. Dennison, Monte Manning
Life of this patent
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Abstract
An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
Claims41
A method of fabricating a bottom and top gated thin film transistor comprising the following steps:
- providing an electrically conductive bottom thin film transistor gate electrode layer on a semiconductor substrate, the bottom gate electrode layer having a planarized outer surface, the outer surface having a surface area;
- providing a bottom gate dielectric layer over the bottom gate electrode layer;
- providing a thin film transistor body layer over the bottom gate layer;
- defining source, drain and channel regions within the thin film body layer;
- providing a top gate dielectric layer over the thin film transistor body layer;
- providing an electrically conductive top transistor gate electrode layer over the top gate dielectric layer;
- etching the composite top gate electrode, top gate dielectric, and body layers in a pattern which defines a top gate electrode, top gate dielectric and body outline which is received only partially within the bottom gate electrode outer surface area, the bottom gate electrode outer surface area including a portion extending outwardly beyond the outline, the etching defining outwardly exposed top gate electrode and body sidewalls;
- providing a layer of insulating dielectric over the etched top gate electrode and outwardly exposed sidewalls;
- anisotropically etching the insulating dielectric layer to define an insulating sidewall spacer, the sidewall spacer leaving the top gate electrode sidewall outwardly exposed;
- outwardly exposing bottom gate electrode surface area extending outwardly beyond the outline;
- providing a layer of electrically conductive material over the outwardly exposed top gate electrode sidewall and outwardly exposed bottom gate electrode surface area;
- and
- anisotropically etching the layer of conducting material to define an electrically conductive sidewall link electrically interconnecting the top gate electrode sidewall and bottom gate electrode outer surface.
10 more elements
An electrical interconnection method comprising:
- providing two conductive layers separated by an insulating material on a semiconductor wafer;
- etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer;
- depositing an electrically conductive material over the etched conductive layers and their respective sidewalls;
- and
- anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers.
2 more elements
An electrical interconnection method comprising:
- providing inner and outer conductive layers separated by an insulating material on a semiconductor wafer;
- etching the conductive layers and insulating material to define and outwardly expose a sidewall of the outer conductive layer and to outwardly expose the inner conductive layer;
- depositing an electrically conductive material over the etched conductive layers, the electrically conductive material contacting the outer conductive layer exposed sidewall and exposed inner conductive layer;
- and
- anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers.
2 more elements
A bottom and top gated thin film transistor comprising:
- a conductive bottom thin film transistor gate electrode, the bottom gate electrode having a planarized outer surface, the outer surface having a surface area;
- a bottom gate dielectric layer atop the bottom gate electrode;
- a thin film transistor body layer over the bottom gate layer, the thin film transistor body layer having source, drain and channel regions, the channel region overlapping with the bottom gate electrode, the channel region having an insulated sidewall;
- a top gate dielectric layer over the thin film transistor body layer;
- an electrically conductive top thin film transistor gate electrode over the top gate dielectric layer, the top gate electrode overlapping with the channel region, the top gate electrode having an electrically conductive sidewall, the bottom gate electrode outer surface area is including a portion extending outwardly beyond the top gate electrode sidewall;
- and
- an electrically conductive sidewall link overlying the electrically insulated channel region sidewall and extending between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes.
4 more elements
An integrated circuit comprising:
- two conductive layers separated by an insulating material on a semiconductor wafer, the conductive layers each having an outer sidewall;
- and
- an electrically conductive sidewall link positioned over and electrically interconnecting the respective outer sidewalls of the two conductive layers.
An integrated circuit comprising:
- inner and outer conductive layers separated by an insulating material on a semiconductor wafer, the outer conductive layer having a sidewall, the inner conductive layer having an outer conductive surface;
- and
- an electrically conductive sidewall link positioned over and electrically interconnecting the outer conductive layer sidewall and inner conductive layer outer conductive surface.
Dependencies are inferred from the claim text.