Device for use in controlling a sample rate
AssigneeAnalog Devices, Inc.
InventorsRichard Schubert, James Wilson, Colm Prendergast
Life of this patent
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Abstract
A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.
Claims28
A communication circuit comprising:
- an all-digital loop circuit to control a clock rate of a digital circuit element to be a function of a frequency of a signal received by the communication circuit.
A circuit comprising:
- a loop circuit to control a sample rate of a digital circuit element.
A device that receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams.
A clock recovery circuit comprising a sample rate converter.
A phase locked loop comprising a sample rate converter.
A device comprising:
- at least one sample rate converter that receives a sampled data stream and outputs two separate data streams having output sample rates that are independent of one another.
A circuit comprising:
- an analog to digital converter clocked at a fixed frequency;
- and
- a loop circuit that receives an output of the analog to digital converter and outputs a sample data stream having a sample rate as a function of a frequency component of a signal received by the circuit.
Dependencies are inferred from the claim text.