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US 2001/0033508 A1Published application
Content addressable memory cells and systems and devices using the same
AssigneeSilicon Aquarius, Inc.
InventorCraig Waller
Life of this patent
Estimating the term…
Abstract
A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.
Claims38
A content addressable memory cell comprising:
- a first storage element for storing information;
- a first transistor for selectively transferring charge representing information from a first bitline to said first storage element;
- a second storage element for storing data;
- a second transistor for selectively transferring charge representing information from a second bitline to said second storage element;
- a first compareline for carrying a first bit of a comparand;
- a second compareline for carrying a second bit of said comparand;
- and
- a plurality of matchlines each for maintaining a result from a comparison between information stored at said storage elements and a comparand presented on said comparelines;
- a comparator for comparing said first and second bits of said comparand with information stored on said first and second storage elements and selectively controlling a voltage on a corresponding one of said plurality of matchlines in response.
6 more elements
A content addressable memory comprising:
- a first pair of bitlines;
- a second pair of bitlines;
- a first memory cell including a first transistor for coupling a first one of said first pair of bitlines to a first data storage node in response to a signal presented on a first wordline and a second transistor for coupling a first one of said second pair of bitlines with said first storage node in response to a signal presented on a second wordline;
- a second memory cell including a first transistor for coupling a second one of said first pair of bitlines to a second data storage node in response to a signal presented on said first wordline and a second transistor for coupling a second one of said second pair of bitlines with said second storage node in response to a signal presented on said second wordline, wherein a first selected one of said first and second pairs of complementary bitlines is operable to access said first and second storage nodes simultaneously with precharge of a second selected one of said first and second pairs of complementary bitlines;
- and
- comparator circuitry for comparing data stored at said first storage node with data presented on a first compareline and data stored at said second storage node with data presented on a second compareline and selectively pulling down a precharged matchline in response.
3 more elements
A content addressable memory cell comprising:
- a first pair of conductors;
- a first storage element;
- a first transistor for selectively coupling said first storage element to a first one of said first pair of conductors and a second transistor for selectively coupling said first storage element to a second one of said first pair of conductors;
- a second pair of conductors;
- a second storage element;
- a third transistor for selectively coupling said second storage element with a first one of said second pair of conductors and a fourth transistor for selectively coupling said second storage element with a second one of said second pair of conductors;
- a first matchline;
- a second matchline;
- first circuitry for selectively comparing data presented on said first one of said first pair of conductors with data stored in said first storage element and data presented on said first one of said second pair of conductors with data stored on said second storage element and selectively pulling down of voltage presented on said first matchline in response;
- and
- second circuitry for selectively comparing data presented on said second one of said first pair of conductors with data stored in said first storage element and data presented on said second one of said second pair of conductors with data stored in said second storage element and selectively pulling down a voltage presented on said second matchline in response.
8 more elements
A content addressable memory comprising:
- a plurality of conductors;
- a plurality memory cells each comprising a storage element and a transistor for selectively coupling said storage element to a corresponding one of said plurality of conductors;
- and
- a plurality of comparator circuits each for comparing a bit of data stored in a said storage element of a selected said memory cell with a bit of a comparand presented on a corresponding one of said plurality of conductors and selectively controlling an associated one of a plurality of matchlines in response.
1 more element
A telecommunications subsystem comprising:
- an input port for receiving a stream of information;
- a plurality of output ports, a selected one of said output ports transmitting said stream of information received by said input port to a next node in a telecommunications network;
- and
- a content addressable memory for storing a translation table, said translation table containing information for selecting said selected one of said output ports, comprising:
- a plurality of conductors;
- a plurality of memory cells each having a first transistor for exchanging charge between a first one of said conductors and a storage element and a second transistor for exchanging charge between said storage element and a second one of said conductors;
- and
- a comparator circuitry for comparing data presented on a selected pair of said plurality of conductors with data stored on said storage elements of a corresponding pair of said memory cells and selectively pulling-down a voltage on an associated matchline.
5 more elements
A binary content addressable memory cell comprising:
- first and second bitlines;
- a first memory cell including a static random access memory cell and a transistor for accessing said storage element through said first bitline in response to a control signal presented on an associated wordline;
- a second memory cell including a static random access memory cell and a transistor for accessing said storage element through said second bitline in response to said control signal presented on said wordline;
- first and second comparelines;
- and
- comparator circuitry for comparing information stored in said memory cell of said first and second memory cells with information presented on said first and second comparelines and selectively controlling a voltage on an associated matchline in response.
3 more elements
Dependencies are inferred from the claim text.