Linear full-rate phase detector and clock and data recovery circuit

An apparatus for recovering data from a received data signal comprising:

• a first storage device configured to generate a first signal by receiving and storing the received data signal;
• a second storage device configured to generate a second signal by receiving and storing the first signal;
• a first delay block configured to generate a third signal by delaying the first signal;
• a third storage device configured to generate a fourth signal by receiving and storing the third signal;
• a second delay block configured to generate a fifth signal by delaying the received data signal;
• a first logic gate configured to perform an exclusive-OR of the second and fourth signals;
• and
• a second logic gate configured to perform an exclusive-OR of the first and fifth signals,
• wherein when the first storage device stores the received data, the second storage device stores the first signal, and the third storage device does not store the third signal, and when the third storage device stores the third signal, the first storage device does not store the received data, and the second storage device does not store the first signal.

An apparatus for recovering data from a received data signal comprising:

• a first flip-flop having a data input coupled to a first data input port, and a clock input coupled to a first clock port;
• a second flip-flop having a data input coupled an output of the first flip-flop, and a clock input coupled to the first clock port;
• a first delay element having an input coupled to the output of the first flip-flop;
• a third flip-flop having a data input coupled to an output of the first delay element, and a clock input coupled to a second clock port;
• a second delay element having an input coupled to the first data input port;
• a first exclusive-OR gate having a first input coupled to the output of the second flip-flop, and a second input coupled to an output of the third flip-flop;
• and
• a second exclusive-OR gate having a first input coupled to the output of the first flip-flop and a second input coupled the second delay element,
• wherein the signal at the second clock port is the complement of the signal at the first clock port.