Jitter detecting circuit for detecting cycle-to-cycle jitter

A jitter detecting circuit for detecting a cycle-to-cycle jitter in a target clock signal comprising at least one jitter detector,

• said at least one jitter detector including
• a phase difference detecting unit comparing said target clock signal with a reference clock signal to see whether or not a phase difference takes place in a certain clock cycle and changing a first output signal between a first logic level representative of a presence of said phase difference and a second logic level representative of an absence of said phase difference, and
• a state change detecting unit storing a logic level of said first output signal in a previous clock cycle, comparing the logic level of said first output signal in said certain clock cycle with the logic level of said first output signal in said previous clock cycle to see whether or not said first output signal changes said logic level between said previous clock cycle and said certain clock cycle and producing a second output signal representative of said cycle-to-cycle jitter when said phase difference detecting unit changes said first output signal between said first logic level and said second logic level.