Method and apparatus for digital to analog converters with improved switched R-2R ladders

A switched m-bit R-2R ladder for conversion of a digital input code into an analog output voltage level on an analog output line, the analog output voltage level a function of a voltage difference between a first and second reference voltage input signal lines, the switched m-bit R-2R ladder comprising:

• a most significant bit (MSB) switch leg for coupling 2m−1/2m of the voltage difference to the analog output line in response to the digital input code, the MSB switch leg comprising a first negative switch and a first positive switch each having a coupling terminal connected to a first end of a first resistance, the first negative switch having a supply terminal connected to the second reference voltage input signal line and a control terminal coupled to an inverted MSB signal of the digital input code, the first positive switch having a supply terminal connected to the first reference voltage input signal line and a control terminal coupled to a non-inverted MSB signal of the digital input code, and the first resistance having a second end coupled to the analog output line, the first negative switch and the first positive switch for selectively coupling substantially 2m−1/2m of the voltage difference onto the analog output line in response to the MSB of the digital input code;
• a least significant bit (LSB) switch leg for coupling ½m of the voltage difference to the analog output line in response to the digital input code, the LSB switch leg comprising a second negative switch and a second positive switch each having a coupling terminal connected to a first end of a second resistance, the second negative switch having a supply terminal connected to the first reference voltage input signal line and a control terminal coupled to an inverted LSB signal of the digital input code, the second positive switch having a supply terminal connected to the second reference voltage input signal line and a control terminal coupled to a non-inverted LSB signal of the digital input code, and the second resistance having a second end coupled to the analog output line, the second negative switch and the second positive switch for selectively coupling substantially ½m of the voltage difference onto the analog output line in response to the LSB of the digital input code;
• a termination leg coupled to the LSB switch leg, the termination leg comprising a third negative switch continuously closed, the third negative switch having a supply terminal connected to the second reference voltage input signal line and a coupling terminal connected to a first end of a third resistance, and a substantially linear ON resistance that may become nonlinear if a voltage drop and a current through the third negative switch become saturated, and the third resistance having a second end coupled to the analog output line, the third negative switch continuously coupling the supply terminal to the coupling terminal;
• and;
• the second resistance and third resistance having a resistance value twice the resistance value of the first resistance to avoid the third negative switch becoming saturated to provide linearity over the voltage difference and the m-bit resolution.

A method of converting a digital signal having m-bits into an analog signal, comprising:

• a) providing a termination leg of an R-2R ladder in parallel with a least significant bit (LSB) leg of the R-2R ladder, the LSB leg having a selectively controlled switch and a four unit first resistor in series, the termination leg having a continuously ON switch and a four unit second resistor in series, the continuously ON switch and the second resistor of the termination leg connected in parallel with the LSB leg to decrease a voltage drop across the continuously ON switch;
• b) selectively generating a ½m voltage of a voltage reference range in the LSB leg in response to an LSB of the digital input signal;
• c) providing a most significant bit (MSB) leg of an R-2R ladder in parallel with the LSB leg and the termination leg, the MSB leg selectively generating a 23−1/2m voltage of the voltage reference range in the MSB leg in response to an MSB of the digital input signal;
• and
• d) summing selectively generated voltages to generate the analog output signal.

A method of reducing conditions for saturation of a transistor termination switch in an R-2R ladder of a digital to analog converter, comprising:

• a) splitting a node where the transistor termination switch and a series resistance couple in series together in an R-2R ladder of the digital to analog converter and in parallel with a second resistance and a second transistor switch coupled in series together, the node split into two parallel nodes such that the second resistance remains coupled to a third resistance in series with the second resistance and is decoupled from the first resistance;
• b) increasing the series resistance of the second and third resistance by a unit resistance and increasing the first resistance by a two unit resistance to reduce the onset of saturation in the transistor termination switch;
• and
• c) coupling the first resistance in parallel with the second and third resistances coupled in series together in the R-2R ladder of the digital to analog converter.