Frequency synthesizer

Abstract

A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.

Dependencies are inferred from the claim text.