US 2001/0033192 A1 · Low-noise four-quadrant multiplier method and apparatus

Abstract

A method for reducing noise in a four-quadrant multiplier having first and second cross-coupled pairs of differential bipolar transistors, differential input current terminals connected with a first pair of common junctions of the respective pairs of differential transistors and the differential output current terminals cross coupled to form a second pair of common junctions of the respective pairs of differential transistors is described. The method includes providing a noise current path from the differential input current terminals to a bias voltage, the noise current path substantially bypassing the differential output current terminals when the gain of the multiplier is near zero. Preferably, the first junctions are common emitter junctions and the second junctions are common collector junctions, and the noise current path comprises a third pair of transistors having respective emitters connected to the common emitter junctions, having common collectors connected to a bias voltage and common bases connected to a controlling voltage. Overall output noise is substantially reduced, as the current through the differential transistor pairs is shunted instead to the bias voltage, effectively ensuring that no noise current reaches the differential output terminals when the current through the differential transistor pairs is zero, i.e. when the gain of the multiplier is zero.

Claims17

Dependent claims

A method of reducing noise in a four-quadrant multiplier having first and second cross-coupled pairs of differential transistors, differential input current terminals connected with a first pair of common junctions of the respective pairs of differential transistors and differential output current terminals cross coupled to form a second pair of common junctions of the respective pairs of differential transistors, the method comprising:

providing a noise current path from the differential input current terminals to a bias voltage, said noise current path substantially bypassing the differential output current terminals when the gain of the multiplier is substantially zero.

In a four-quadrant multiplier comprising a first differential transistor pair Q1/Q2 having emitters connected together to form an emitter junction connected in turn to a first differential input terminal, with Q1 having a collector connected to a first differential output terminal and with Q2 having a collector connected to a second differential output terminal, a second differential transistor pair Q3/Q4 having emitters connected together to form an emitter junction connected in turn to a second differential input terminal, with Q3 having a collector connected to said first differential output terminal and with Q4 having a collector connected to said second differential output terminal wherein the bases of transistors Q2 and Q3 are connected in common to a first control voltage and the bases of transistors Q1 and Q4 being connected in common to a second control voltage, the improvement comprising:

a transistor pair Q5 and Q6 operatively connected to said first and second differential transistor pairs Q1/Q2 and Q3/Q4, respectively, said transistor pair Q5 and Q6 having collectors connected to a bias voltage,
emitters of said transistor pair Q5 and Q6 connected in common with the emitters of the respective differential transistor pairs to said first and second differential input terminals, and
bases of said transistor pair Q5 and Q6 connected in common to a third control voltage,
said transistor pair Q5 and Q6 conducting current from the emitter junctions of the respective differential transistor pairs to the bias voltage thereby to achieve low noise at low gain.

1 more element

In four-quadrant multiplier apparatus comprising a first differential transistor pair Qi/Q2 having sources connected together to form a source junction connected in turn to a first differential input terminal, with Q1 having a drain connected to a first differential output terminal and with Q2 having a drain connected to a second differential output terminal, a second differential transistor pair Q3/Q4 having sources connected together to form a source junction connected in turn to a second differential input terminal, with Q3 having a drain connected to said first differential output terminal and with Q4 having a drain connected to said second differential output terminal wherein the gates of transistors Q2 and Q3 are connected in common to a first control voltage and the gates of transistors Q1 and Q4 are connected in common to a second control voltage, the improvement comprising:

a transistor pair Q5 and Q6 operatively connected to said first and second differential transistor pairs Q1/Q2 and Q3/Q4, respectively, said transistor pair Q5 and Q6 having drains connected to a bias voltage,
sources of said transistor pair Q5 and Q6 connected in common with the sources of the respective differential transistor pairs to said first and second differential input terminals, and
gates of said transistor pair Q5 and Q6 connected in common to a third control voltage,
said transistor pair Q5 and Q6 conducting current from the source junctions of the respective differential transistor pairs to the bias voltage thereby to achieve low noise at low gain.

1 more element

Dependencies are inferred from the claim text.

Low-noise four-quadrant multiplier method and apparatus

Life of this patent

Low-noise four-quadrant multiplier method and apparatus

Life of this patent

Abstract

Claims17