Conflict free radiation tolerant storage cell
AssigneeUniversity of New Mexico
InventorsGary Maki, Kenneth Hass, Shi Quan, James Murguia
Life of this patent
Estimating the term…
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AssigneeUniversity of New Mexico
InventorsGary Maki, Kenneth Hass, Shi Quan, James Murguia
Estimating the term…
A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-2 State Table.
A Single Event Upset (SEU) resistant latch circuit SERT-1 comprising:
A Single Event Upset (SEU) resistant latch circuit SERT-2 comprising:
Dependencies are inferred from the claim text.