Regenerative signal level converter
AssigneeBroadcom Corporation
InventorMichael M. Green
Life of this patent
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Abstract
Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a CMOS latch.
Claims19
A complementary metal-oxide-semiconductor (CMOS) circuit for converting a differential logic signal to a single-ended logic signal, comprising:
- a differential input stage coupled to receive the differential logic signal and configured to steer current into a first output branch or a second output branch in response to the differential logic signal;
- a first output transistor coupled to the first output branch;
- a second output transistor coupled to the second output branch;
- and
- a CMOS latch coupled between the first output transistor and the second output transistor.
A complementary metal-oxide-semiconductor (CMOS) circuit for converting a differential logic signal to a single-ended logic signal, comprising:
- an input stage having first and second differential input terminals and first and second output terminals;
- and
- a CMOS latch having a first node coupled to the first output terminal and a second node coupled to the second output terminal,
- wherein, the input stage receives the differential logic signal at its first and second differential input terminals, and the circuit is configured to generate a self-regulating current pulse at one of the first and second nodes of the CMOS latch in response to the differential logic signal.
A complementary metal-oxide-semiconductor (CMOS) circuit comprising:
- a first circuit implemented in current-controlled CMOS (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;
- a differential signal to single-ended signal converter coupled to the first circuit, the converter having a CMOS latch that is configured to switch states in response to a self-regulating current pulse that is generated in response to the differential input signal, thereby converting the differential signal from the first circuit to a single-ended CMOS logic signal;
- and
- a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in standard CMOS logic wherein substantially zero static current is dissipated.
A method of converting a differential logic signal to a single-ended logic signal comprising:
- receiving a differential logic signal at inputs of a differential input circuit;
- generating a current pulse at one of two outputs of the differential pair in response to the differential logic signal;
- and
- switching the state of a regenerative CMOS latch in response to the current pulse.
Dependencies are inferred from the claim text.