Ball array layout and method of making

A chip assembly, comprising:

• a plurality of ball pads, each:
• having an electrically conductive trace connected thereto;
• having a maximum width;
• and
• being upon a substrate having two sets of opposing parallel edges that form a rectilinear closed periphery;
• a plurality of buffer traces upon the substrate, wherein:
• the plurality of ball pads are situated within the rectilinear closed periphery;
• each ball pad is no closer to any of said buffer traces than a minimum distance, and wherein the minimum distance is less than the ball pad maximum width;
• each said ball pad has a perimeter with a length;
• the ball pads are arranged into a first column that is parallel to a second column;
• each ball pad in the first column is adjacent to a first buffer trace of said buffer traces;
• each ball pad in the second column is adjacent to a second buffer trace of said buffer traces;
• a first portion of the length of the periphery of each ball pad in the first column is parallel to said first buffer trace;
• a second portion of the length of the periphery of each ball pad in the second column is parallel to said second buffer trace;
• and
• the first portion is greater than the second portion;
• and
• a semiconductive-material-comprising chip attached to said substrate.

A chip assembly, comprising:

• a substrate having two sets of parallel edges forming a rectilinear periphery;
• a bond wire pad column upon the substrate and comprising a plurality of bond wire pads;
• a ball array upon the substrate and comprising a plurality of ball pads each having a minimum diameter, said ball array being configured in a rectangular space and having an outer ball column that is parallel with one of said two sets of parallel edges;
• at least one buffer trace upon the substrate, wherein the outer ball column is closer to the rectilinear periphery that is parallel thereto than any of the at least one buffer trace;
• an elongated, symmetrical slot in the substrate, the slot having a major axis, wherein the major axis is parallel to one of the two sets of parallel edges, wherein each buffer trace is closer to the slot than said one of two sets of parallel edges;
• and
• a semiconductive-material-comprising chip attached to said substrate.