Semiconductor memory having a memory cell array
AssigneeInfineon Technologies AG
InventorFranz Hofmann
Life of this patent
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Abstract
A semiconductor memory such as, for example, a DRAM (Dynamic Random Access Memory) includes a memory cell array and an addressing periphery. A first memory cell having a first selection transistor and a first storage capacitor, and a second memory cell having a second selection transistor and a second storage capacitor are configured in the memory cell array. The first selection transistor is designed as an n-channel transistor and the second selection transistor is designed as a p-channel transistor. This makes it possible to realize a folded bit line concept for memory cells which are smaller than 8F2.
Claims15
A semiconductor memory having a memory cell array, the memory cell array comprising:
- a silicon on insulator substrate having an insulation layer;
- a first memory cell having a first storage capacitor and a first selection transistor formed as an n-channel transistor;
- and
- a second memory cell having a second storage capacitor and a second selection transistor formed as a p-channel transistor;
- said first memory cell and said second memory cell formed in said silicon on insulator substrate.
Dependencies are inferred from the claim text.