# US 2001/0026488 A1 · Semiconductor memory and method of saving energy of the memory

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- Number: US 2001/0026488 A1
- Document ID: US20010026488A1
- Status: Published application
- Kind: A1
- Application number: 09/819,352
- Filed: 2001-03-28
- Published: 2001-10-04
- Earliest claimed: 2000-03-30
- Assignees: NEC Corporation
- Inventors: Naohisa Nishioka
- Web page: https://patentgrep.com/patent/US20010026488A1

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In an array of memory cells, multiple prechargers are respectively connected to bit-line pairs of the array. Near-end balancers and far-end balancers are connected to opposite ends of the bit-line pairs. During a read mode of the memory, the prechargers and both near-end and far-end balancers are activated. For power savings purposes, during a write mode the prechargers and the far-end balancers remain inactive and the near-end balancers are activated.

## Claims

### Claim 1

A semiconductor memory comprising an array of memory cells, a plurality of bit-line pairs to which the memory cells of said array are connected, and a plurality of prechargers respectively connected to said bit-line pairs, characterized in that said prechargers are active during a read mode of the memory and remain inactive during a write mode of the memory

### Claim 2 (depends on 1)

A semiconductor memory as claimed in claim 1, further characterized by a first plurality of balancers connected respectively to first ends of said bit-line pairs and a second plurality of balancers connected respectively to second, opposite ends of said bit-line pairs, wherein said first plurality of balancers are active during said read and write modes and said second plurality of balancers are active during said read mode and remain inactive during said write mode.

### Claim 3 (depends on 2)

A semiconductor memory as claimed in claim 2, characterized in that each of said prechargers further includes a balancing transistor connected across the bit lines of a corresponding pair, said balancing transistor being active at least during said write mode.

### Claim 4

A semiconductor memory comprising:
an array of memory cells;
a plurality of bit-line pairs to which the memory cells of said array are connected;
a plurality of prechargers respectively connected to said bit-line pairs; and
control circuitry for supplying energy to said prechargers for charging said bit-line pairs exclusively during a read mode of said memory.

### Claim 5 (depends on 4)

A semiconductor memory as claimed in claim 4, further comprising:
a first plurality of balancers connected respectively to first ends of said bit-line pairs; and
a second plurality of balances connected respectively to second, opposite ends of said bit-line pairs,
said control circuitry supplying energy to said first plurality of balancers and said second plurality of balancers during said read mode of said memory and exclusively supplying energy to said first plurality of balancers during a write mode of said memory.

### Claim 6 (depends on 5)

A semiconductor memory as claimed in claim 5, wherein each of said prechargers further includes a balancing transistor connected across the bit lines of a corresponding pair, said balancing transistor being active at least during said write mode.

### Claim 7

A method of saving energy consumption of a semiconductor memory comprising an array of memory cells, a plurality of bit-line pairs to which the memory cells of said array are connected, and a plurality of prechargers respectively connected to said bit-line pairs, the method comprising the step of supplying energy to said prechargers exclusively during a read mode of the memory.

### Claim 8 (depends on 7)

The method of claim 7, wherein said memory further comprises a first plurality of balancers connected respectively to first ends of said bit-line pairs, and a second plurality of balancers connected respectively to second, opposite ends of said bit-line pairs, further comprising the steps of supplying energy to said first plurality of balancers and said second plurality of balancers during said read made of said memory and exclusively supplying energy to said first plurality of balancers during a write mode of said memory.

### Claim 9 (depends on 8)

The method of claim 8, further comprising the step of establishing a semiconductor path between the bit-line of each of said pairs at least during said write mode.